Patents by Inventor Joo Ho Jung
Joo Ho Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145118Abstract: A transparent conductor according to an exemplary embodiment of the present invention includes a transparent substrate, and a transparent conductive pattern formed on the transparent substrate, and the transparent conductor includes a nanostructure on an upper surface of at least one of the transparent substrate and the transparent conductive pattern.Type: ApplicationFiled: March 17, 2021Publication date: May 2, 2024Inventors: Dae-Guen CHOI, Hyuk Jun KANG, Ji Hye LEE, Junhyuk CHOI, Won Seok CHANG, Joo Yun JUNG, Jun-ho JEONG
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Publication number: 20230378174Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.Type: ApplicationFiled: August 3, 2023Publication date: November 23, 2023Inventors: Sang Min YOO, Ju Youn KIM, Hyung Joo NA, Bong Seok SUH, Joo Ho JUNG, Eui Chul HWANG, Sung Moon LEE
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Patent number: 11784186Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.Type: GrantFiled: August 3, 2021Date of Patent: October 10, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Min Yoo, Ju Youn Kim, Hyung Joo Na, Bong Seok Suh, Joo Ho Jung, Eui Chui Hwang, Sung Moon Lee
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Patent number: 11538807Abstract: A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending in the second direction on the active pattern and the field insulating film; and a first device isolation film between the first and second gate structure, wherein a side wall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle with respect to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.Type: GrantFiled: May 12, 2021Date of Patent: December 27, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eui Chul Hwang, Ju Youn Kim, Hyung Joo Na, Bong Seok Suh, Sang Min Yoo, Joo Ho Jung, Sung Moon Lee
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Publication number: 20210366905Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.Type: ApplicationFiled: August 3, 2021Publication date: November 25, 2021Inventors: Sang Min YOO, Ju Youn KIM, Hyung Joo NA, Bong Seok SUH, Joo Ho JUNG, Eui Chul HWANG, Sung Moon LEE
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Publication number: 20210265351Abstract: A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending in the second direction on the active pattern and the field insulating film; and a first device isolation film between the first and second gate structure, wherein a side wall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle with respect to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.Type: ApplicationFiled: May 12, 2021Publication date: August 26, 2021Inventors: Eui Chul Hwang, Ju Youn Kim, Hyung Joo Na, Bong Seok Suh, Sang Min Yoo, Joo Ho Jung, Sung Moon Lee
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Patent number: 11101269Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.Type: GrantFiled: September 18, 2020Date of Patent: August 24, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Min Yoo, Ju Youn Kim, Hyung Joo Na, Bong Seok Suh, Joo Ho Jung, Eui Chui Hwang, Sung Moon Lee
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Patent number: 11063150Abstract: A semiconductor device may include active fins each of which extends in a first direction on a substrate, the active fins being spaced apart from each other in a second direction different from the first direction, a conductive structure extending in the second direction on the substrate, the conductive structure contacting the active fins, a first diffusion break pattern between the substrate and the conductive structure, the first diffusion break pattern dividing a first active fin of the active fins into a plurality of pieces aligned in the first direction, and a second diffusion break pattern adjacent to the conductive structure on the substrate, the second diffusion break pattern having an upper surface higher than a lower surface of the conductive structure, and dividing a second active fin of the active fins into a plurality of pieces aligned in the first direction.Type: GrantFiled: May 15, 2019Date of Patent: July 13, 2021Assignee: SAMSUNG ELECTRONICS CO. LTD.Inventors: Sang-Min Yoo, Byung-Sung Kim, Ju-Youn Kim, Bong-Seok Suh, Hyung-Joo Na, Sung-Moon Lee, Joo-Ho Jung, Eui-Chul Hwang
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Patent number: 11011519Abstract: A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending in the second direction on the active pattern and the field insulating film; and a first device isolation film between the first and second gate structure, wherein a side wall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle with respect to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.Type: GrantFiled: March 29, 2019Date of Patent: May 18, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eui Chul Hwang, Ju Youn Kim, Hyung Joo Na, Bong Seok Suh, Sang Min Yoo, Joo Ho Jung, Sung Moon Lee
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Publication number: 20210005603Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.Type: ApplicationFiled: September 18, 2020Publication date: January 7, 2021Inventors: Sang Min YOO, Ju Youn KIM, Hyung Joo NA, Bong Seok SUH, Joo Ho JUNG, Eui Chul HWANG, Sung Moon LEE
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Patent number: 10804265Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.Type: GrantFiled: April 12, 2019Date of Patent: October 13, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Min Yoo, Ju Youn Kim, Hyung Joo Na, Bong Seok Suh, Joo Ho Jung, Eui Chul Hwang, Sung Moon Lee
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Patent number: 10636793Abstract: A FINFET includes a first fin extending in a first direction on a substrate and, a second fin extending in the first direction and spaced apart from the first fin in the first direction. A third fin is provided with a long side shorter than long sides of the first fin and the second fin and is disposed between the first fin and the second fin. A first gate structure extends in a second direction different from the first direction and crosses the first fin. A device isolation layer is disposed on a lower sidewall of each of the first, second and third fins and is formed to extend in the first direction. An electrically insulating diffusion break region includes a first portion crossing between the first fin and the third fin, a second portion crossing between the second fin and the third fin, and a third portion disposed between the first portion and the second portion on the third fin. The diffusion break region extends in the second direction on the device isolation layer.Type: GrantFiled: November 29, 2018Date of Patent: April 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung Joo Na, Ju Youn Kim, Bong Seok Suh, Sang Min Yoo, Joo Ho Jung, Eui Chul Hwang, Sung Moon Lee
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Publication number: 20200105919Abstract: A semiconductor device may include active fins each of which extends in a first direction on a substrate, the active fins being spaced apart from each other in a second direction different from the first direction, a conductive structure extending in the second direction on the substrate, the conductive structure contacting the active fins, a first diffusion break pattern between the substrate and the conductive structure, the first diffusion break pattern dividing a first active fin of the active fins into a plurality of pieces aligned in the first direction, and a second diffusion break pattern adjacent to the conductive structure on the substrate, the second diffusion break pattern having an upper surface higher than a lower surface of the conductive structure, and dividing a second active fin of the active fins into a plurality of pieces aligned in the first direction.Type: ApplicationFiled: May 15, 2019Publication date: April 2, 2020Inventors: Sang-Min YOO, Byung-Sung KIM, Ju-Youn KIM, Bong-Seok SUH, Hyung-Joo NA, Sung-Moon LEE, Joo-Ho JUNG, Eui-Chul HWANG
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Publication number: 20200043920Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.Type: ApplicationFiled: April 12, 2019Publication date: February 6, 2020Inventors: Sang Min YOO, Ju Youn KIM, Hyung Joo NA, Bong Seok SUH, Joo Ho JUNG, Eui Chul HWANG, Sung Moon LEE
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Publication number: 20200043929Abstract: A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending in the second direction on the active pattern and the field insulating film; and a first device isolation film between the first and second gate structure, wherein a side wall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle with respect to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.Type: ApplicationFiled: March 29, 2019Publication date: February 6, 2020Inventors: Eui Chul HWANG, Ju Youn KIM, Hyung Joo NA, Bong Seok SUH, Sang Min YOO, Joo Ho JUNG, Sung Moon LEE
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Publication number: 20190393220Abstract: A FINFET includes a first fin extending in a first direction on a substrate and, a second fin extending in the first direction and spaced apart from the first fin in the first direction. A third fin is provided with a long side shorter than long sides of the first fin and the second fin and is disposed between the first fin and the second fin. A first gate structure extends in a second direction different from the first direction and crosses the first fin. A device isolation layer is disposed on a lower sidewall of each of the first, second and third fins and is formed to extend in the first direction. An electrically insulating diffusion break region includes a first portion crossing between the first fin and the third fin, a second portion crossing between the second fin and the third fin, and a third portion disposed between the first portion and the second portion on the third fin. The diffusion break region extends in the second direction on the device isolation layer.Type: ApplicationFiled: November 29, 2018Publication date: December 26, 2019Inventors: Hyung Joo Na, Ju Youn Kim, Bong Seok Suh, Sang Min Yoo, Joo Ho Jung, Eui Chul Hwang, Sung Moon Lee