Abstract: A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region.

Abstract: A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region.

Abstract: A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region.

Abstract: A pattern formation method of a semiconductor device, and to a manufacturing method of a flash memory, in which spacer patterning technology is performed while two hard mask layers having a different etching characteristics are used, such that the patterning can be performed by using only a spacer as a mask in the region which requires a small pattern. Additionally, the patterning can be performed by using a hard mask layer pattern and the spacer as a mask in a region which requires a large pattern. Therefore, the pattern formation method of the invention can be used to form a semiconductor device with patterns having various sizes using just a single patterning.

Abstract: A film mode video sequence detector for detecting video sequences converted from movie films in 30 Hz frame rate video resources comprises a video signal detecting means provided a mean of absolute difference (MAD) value of input video signal and a film mode condition generation signal considering a user threshold and still picture, making a decision whether the input signal is film mode, and transmitting the film mode condition generation signal, film mode departure signal, the threshold pass signal, and a clock which is generated on film mode condition; a condition generating means provided the MAD value and the condition generating signal from the video mode detecting means, making a decision whether the MAD value shows a pattern off film mode considering still picture, transmitting the film mode condition generating signal to the video signal detecting means; a mode converting means provided an input field decision signal, a screen transition generating signal, departure signal from video mode decision me

Abstract: An apparatus for estimating a half-pel motion comprising: a memory for storing motion-compensation errors in integer-pel positions; an address generator for generating an address of the integer-pel positions to the memory; an operator for receiving the motion-compensation errors from the memory, and calculating motion-compensation errors in the eight half-pel positions which are on the outskirts of the integer-pel position having a minimum motion-compensation error; and a comparator and half-pel motion vector selector for comparing the motion-compensation errors in the eight half-pel positions with the minimum motion-compensation error in the integer-pel position and selecting a position having a minimum motion-compensation error as a final half-pel motion vector.

Abstract: An NTSC/PAL video signal conversion apparatus employing a ITU-R BT.