Patents by Inventor Joo Hun Park
Joo Hun Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145790Abstract: A button-type secondary battery includes a lower can having a bottom surface; an upper can having a top, the upper can and the lower can being coupled to define a space therein; an electrolyte in the space; an electrode assembly in the space and including a negative electrode, a separator, and a positive electrode wound together; a gasket between the upper can and the lower can to electrically insulate the upper and lower cans; a top insulator that is electrically insulating and covering a top surface of the electrode assembly; and a bottom insulator that is electrically insulating and covering a bottom surface of the electrode assembly. The top and bottom insulators are each configured to expand in volume by absorbing the electrolyte. Surfaces of at least one of the top insulator and the bottom insulator are coated with a protective layer to prevent thermal shrinkage from occurring.Type: ApplicationFiled: October 14, 2022Publication date: May 2, 2024Applicant: LG ENERGY SOLUTION, LTD.Inventors: Yeong Hun JUNG, Young Ji TAE, Joo Hwan SUNG, Min Su CHO, Geun Young PARK, Min Gyu KIM, Min Seon KIM, Sang Hak CHAE, Min Young JU
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Publication number: 20240128554Abstract: A button type secondary battery includes a wound electrode assembly; a lower can with the electrode assembly and an electrolyte in the lower can; a top plate to close the lower can; a positive electrode terminal coupled to the top plate through a gasket to be electrically insulated from the top plate with a portion of the positive electrode terminal passing through a hole in the top plate to be bonded to a positive electrode tab; a top insulator covering a top surface of the electrode assembly; and a bottom insulator covering a bottom surface of the electrode assembly. The top insulator and the bottom insulator are each configured to expand in volume by absorbing the electrolyte. Surfaces of at least one or more of the top insulator and the bottom insulator are coated with a protective layer configured to prevent thermal shrinkage from occurring.Type: ApplicationFiled: October 14, 2022Publication date: April 18, 2024Applicant: LG ENERGY SOLUTION, LTD.Inventors: Yeong Hun JUNG, Young Ji TAE, Joo Hwan SUNG, Min Su CHO, Geun Young PARK, Min Gyu KIM, Min Seon KIM, Sang Hak CHAE, Min Young JU
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Patent number: 11913773Abstract: The present invention relates to a method of non-destructively measuring a thickness of a reinforcement membrane, and more particularly, to a method of non-destructively measuring a thickness of a hydrogen ion exchange reinforcement membrane for a fuel cell, in which the reinforcement membrane has a symmetric three-layer structure including a reinforcement base layer and pure water layers disposed at opposing sides of the reinforcement base layer, including performing total non-destructive inspection and omitting a process of analyzing a position by means of a thickness peak of a power spectrum of the respective layers of the reinforcement membrane.Type: GrantFiled: May 20, 2019Date of Patent: February 27, 2024Assignee: LG CHEM, LTD.Inventors: Sung-Hyun Yun, Joo-Yong Park, Ji-Hun Kim, Jae-Choon Yang
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Patent number: 10546827Abstract: A flip chip includes a substrate, an electrode pad layer stacked over the substrate, a passivation layer stacked at both ends of the electrode pad layer, an under bump metallurgy (UBM) layer stacked over the electrode pad layer and the passivation layer, and a bump formed over the UBM layer. The width of an opening on which the passivation layer is not formed over the electrode pad layer is greater than the width of the bump. The flip chip can prevent a crack from being generated in the pad upon ultrasonic bonding.Type: GrantFiled: June 8, 2017Date of Patent: January 28, 2020Assignee: WISOL CO., LTD.Inventors: Young Seok Shim, Hyung Ju Kim, Joo Hun Park, Chang Dug Kim
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Publication number: 20170358546Abstract: A flip chip includes a substrate, an electrode pad layer stacked over the substrate, a passivation layer stacked at both ends of the electrode pad layer, an under bump metallurgy (UBM) layer stacked over the electrode pad layer and the passivation layer, and a bump formed over the UBM layer. The width of an opening on which the passivation layer is not formed over the electrode pad layer is greater than the width of the bump. The flip chip can prevent a crack from being generated in the pad upon ultrasonic bonding.Type: ApplicationFiled: June 8, 2017Publication date: December 14, 2017Inventors: Young Seok SHIM, Hyung Ju KIM, Joo Hun PARK, Chang Dug KIM
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Patent number: 7820468Abstract: Disclosed herein is a stack type surface acoustic wave package. The surface acoustic wave package comprises a first bare chip having a plurality of electrodes formed thereon, a second bare chip having a plurality of electrodes and via-holes formed thereon, a connecting portion electrically connecting the first bare chip to an upper surface of the second bare chip such that the electrodes of the first bare chip face the electrodes of the second bare chip, and a sealing member provided on the first and second bare chips to form an air-tight space on an operating surface between the first and second bare chips. The surface acoustic wave package can prevent deformation due to thermal impact from the outside during a packaging process, enhancing reliability of the product, minimizing the size of the product, and reducing manufacturing costs by reducing the number of components and material costs.Type: GrantFiled: August 24, 2009Date of Patent: October 26, 2010Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Hee Lee, Doo Cheol Park, Joo Hun Park, Young Jin Lee, Sang Wook Park, Nam Hyeong Kim
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Publication number: 20100047949Abstract: Disclosed herein is a stack type surface acoustic wave package. The surface acoustic wave package comprises a first bare chip having a plurality of electrodes formed thereon, a second bare chip having a plurality of electrodes and via-holes formed thereon, a connecting portion electrically connecting the first bare chip to an upper surface of the second bare chip such that the electrodes of the first bare chip face the electrodes of the second bare chip, and a sealing member provided on the first and second bare chips to form an air-tight space on an operating surface between the first and second bare chips. The surface acoustic wave package can prevent deformation due to thermal impact from the outside during a packaging process, enhancing reliability of the product, minimizing the size of the product, and reducing manufacturing costs by reducing the number of components and material costs.Type: ApplicationFiled: August 24, 2009Publication date: February 25, 2010Applicant: SAMSUNG ELECTRO-MECHANICS CO.,LTD.Inventors: Seung Hee Lee, Doo Cheol Park, Joo Hun Park, Young Jin Lee, Sang Wook Park, Nam Hyeong Kim
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Patent number: 7336017Abstract: A surface acoustic wave package comprises a first bare chip having a plurality of electrodes formed thereon, a second bare chip having a plurality of electrodes and via-holes formed thereon, a connecting portion electrically connecting the first bare chip to an upper surface of the second bare chip such that the electrodes of the first bare chip face the electrodes of the second bare chip, and a sealing member provided on the first and second bare chips to form an air-tight space on an operating surface between the first and second bare chips.Type: GrantFiled: September 2, 2005Date of Patent: February 26, 2008Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Hee Lee, Doo Cheol Park, Joo Hun Park, Young Jin Lee, Sang Wook Park, Nam Hyeong Kim
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Publication number: 20070145541Abstract: Disclosed herein is a stack type surface acoustic wave package. The surface acoustic wave package comprises a first bare chip having a plurality of electrodes formed thereon, a second bare chip having a plurality of electrodes and via-holes formed thereon, a connecting portion electrically connecting the first bare chip to an upper surface of the second bare chip such that the electrodes of the first bare chip face the electrodes of the second bare chip, and a sealing member provided on the first and second bare chips to form an air-tight space on an operating surface between the first and second bare chips. The surface acoustic wave package can prevent deformation due to thermal impact from the outside during a packaging process, enhancing reliability of the product, minimizing the size of the product, and reducing manufacturing costs by reducing the number of components and material costs.Type: ApplicationFiled: March 6, 2007Publication date: June 28, 2007Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Hee LEE, Doo Cheol PARK, Joo Hun PARK, Young Jin LEE, Sang Wook PARK, Nam Hyeong KIM
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Patent number: 7045385Abstract: A method for fabricating Surface Acoustic Wave filter packages uses a package sheet having an outline pattern and anti-bur holes. In the package sheet for a Surface Acoustic Wave filter package, the outline pattern is formed along outer peripheries of chip mounting areas where a plurality of SAW filter chips are to be mounted. The outline pattern is contacted with a metal shield layer formed on the SAW filter chips and a predetermined region of the package sheet. Circular anti-bur holes are located at the corners of the chip mounting areas and on cutting lines along which the sheet is to be singulated into individual SAW filter packages.Type: GrantFiled: November 17, 2003Date of Patent: May 16, 2006Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Tae Hoon Kim, Ju Weon Seo, Joo Hun Park, Moon Soo Jeon
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Patent number: 6928719Abstract: A method for fabricating a surface acoustic wave filter chip package includes: mounting a surface acoustic wave filter chip on a substrate; forming a underfill in a space between the substrate and the chip; forming a metal shield layer on a whole outer wall of the chip by using a spray process; and molding resins on the metal shield layer. The metal shield layer is formed from a conductive epoxy with the use of a spray nozzle.Type: GrantFiled: April 11, 2002Date of Patent: August 16, 2005Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Tae Hoon Kim, Chan Wang Park, Joo Hun Park, Jong Tae Kim
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Patent number: 6670206Abstract: Disclosed is a method for simply fabricating plural surface acoustic wave filter chip packages in large quantities comprising the steps of providing a wafer, on the surface of which plural surface acoustic wave filter chips are formed, and a package substrate, on the surface of which mounting portions corresponding to surface acoustic wave filter chips are formed; providing underfill on the package substrate; mounting the wafer on the package substrate; removing wafer portions between surface acoustic wave filter chips; forming metal shield layers on outer walls of separated surface acoustic wave filter chips; molding a resin on outer walls of surface acoustic wave filter chips coated with metal layers; and dividing the package substrate molded with resin into individual surface acoustic wave filter chip packages.Type: GrantFiled: April 11, 2002Date of Patent: December 30, 2003Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Tae Hoon Kim, Chan Wang Park, Joo Hun Park, Jae Myung Kim
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Publication number: 20030109077Abstract: Disclosed is a method for simply fabricating plural surface acoustic wave filter chip packages in large quantities comprising the steps of providing a wafer, on the surface of which plural surface acoustic wave filter chips are formed, and a package substrate, on the surface of which mounting portions corresponding to surface acoustic wave filter chips are formed; providing underfill on the package substrate; mounting the wafer on the package substrate; removing wafer portions between surface acoustic wave filter chips; forming metal shield layers on outer walls of separated surface acoustic wave filter chips; molding a resin on outer walls of surface acoustic wave filter chips coated with metal layers; and dividing the package substrate molded with resin into individual surface acoustic wave filter chip packages.Type: ApplicationFiled: April 11, 2002Publication date: June 12, 2003Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Tae Hoon Kim, Chan Wang Park, Joo Hun Park, Jae Myung Kim
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Publication number: 20030009864Abstract: Disclosed is a method for fabricating a surface acoustic wave filter chip package comprising the steps of mounting the surface acoustic wave filter chip on a substrate; forming a underfill in a space between the substrate and the surface acoustic wave filter chip; forming a metal shield layer on an whole outer wall of the surface acoustic wave filter chip by using a spray process; and molding resins on the metal shield layer. The method has advantages in that a fillet forming step for improving a step-coverage is removed by forming a metal shield layer from a conductive epoxy with the use of a spray nozzle, a one-ply metal shield layer is formed without an additional metal layer for preventing oxidation of the metal layer by forming an exterior of the SAW filter chip package with the use of a top molding process, and that a structurally stable SAW filter package can be fabricated.Type: ApplicationFiled: April 11, 2002Publication date: January 16, 2003Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Tae Hoon Kim, Chan Wang Park, Joo Hun Park, Jong Tae Kim