Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.

Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.

Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.

Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.

Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.

Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.

Abstract: A shunt regulator includes a control circuit, a bypass circuit and a protection circuit. The control circuit is coupled between a first node and a ground, and generates a gate control signal in response to a voltage of the first node and a reference voltage. The bypass circuit forms a first current path between the first node and the ground in response to the gate control signal. The protection circuit has an MOS transistor that is fully turned on in response to a current flowing through the bypass circuit, and forms a second current path between the first node and the ground. Therefore, the shunt regulator occupies a relatively small area in an integrated circuit.

Abstract: There are provided a pad for touch panel and a touch panel using the same, and more particularly, a pad for touch panel comprising an insulating layer with a conductive pattern wherein the insulating layer has a touch pattern and a lead wire formed on the top surface thereof, and one terminal of the lead wire is extended to an edge of the insulating layer to form a connection electrode, characterized in that the pad for touch panel at least comprises i) an insulating layer with conductive pattern comprising the insulating layer, a transparent conductive coating layer pattern which is partially laminated on the top of the insulating layer and has the touch pattern, the lead wire and the connection electrode pattern thereon, and a metal coating layer which is partially laminated on the top of the transparent conductive coating layer and has the lead wire and the connection electrode pattern thereon; ii) an adhesive layer which is laminated on the top of the insulating layer with conductive pattern; and iii) a c

Abstract: A semiconductor device and a method of fabricating a semiconductor device that includes forming an interlayer insulating film on a semiconductor substrate; depositing a first soft magnetic thin film on the interlayer insulating film through sputtering using a target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; forming a metal film on the first soft magnetic thin film; depositing a second soft magnetic thin film on the metal film through sputtering using the same or another target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; and patterning to form an inductor.

Abstract: A semiconductor device and a method of fabricating a semiconductor device that includes forming an interlayer insulating film on a semiconductor substrate; depositing a first soft magnetic thin film on the interlayer insulating film through sputtering using a target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; forming a metal film on the first soft magnetic thin film; depositing a second soft magnetic thin film on the metal film through sputtering using the same or another target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; and patterning to form an inductor.

Abstract: A semiconductor device includes an interlayer insulating film and an inductor. The inductor includes a first soft magnetic thin film pattern formed on the interlayer insulating film, the first soft magnetic film comprising a) at least one material selected from Fe, Co, Ni, or alloys thereof b) at least one element selected from Ti, Hf, or B, and c) N, a metal film pattern formed on the first soft magnetic thin film pattern and a second soft magnetic thin film pattern formed on the metal film pattern, the second soft magnetic thin film pattern comprising a) at least one material selected from Fe, Co, Ni, or alloys thereof; b) at least one element selected from Ti, Hf, or B; and c) N. Edges of the first soft magnetic thin film pattern, edges of the metal film pattern and edges of the second soft magnetic thin film pattern are vertically aligned.

Abstract: A shunt regulator includes a control circuit, a bypass circuit and a protection circuit. The control circuit is coupled between a first node and a ground, and generates a gate control signal in response to a voltage of the first node and a reference voltage. The bypass circuit forms a first current path between the first node and the ground in response to the gate control signal. The protection circuit has an MOS transistor that is filly turned on in response to a current flowing through the bypass circuit, and forms a second current path between the first node and the ground. Therefore, the shunt regulator occupies a relatively small area in an integrated circuit.

Abstract: An inductor pattern is formed on a substrate. A conductive pattern having a concave-convex structure is formed on the inductor pattern to increase a surface area of the inductor pattern. An insulation layer is formed on the inductor pattern. After a groove is formed such that the insulation layer is removed to expose the inductor pattern, a conductive pattern is conformally formed on the groove and the insulation layer. Thus, a surface area of the inductor pattern as well as a thickness of an inductor increases to obtain an inductor of a high quality factor.

Abstract: Provided is an inductor of a semiconductor device. The inductor may include a current entrance section, multiple layered ring-shaped conductive wires, and a via plug. Each of the ring-shaped conductive wires may be a helical type multi turn ring-shaped wire formed in one plane. The via plug may be connected to at least one of the ring-shaped conductive wires in order to transmit an electrical signal to another ring-shaped conductive wire.

Abstract: In a method of forming a trench structure having a wide void therein, a first trench having a first width and a first depth is formed in a substrate. The first trench is filled with a first insulation layer pattern defining the void in the first trench. A second trench is formed on the first trench. The second trench has a second width wider than the first width and a second depth shallower than the first depth. The second trench is filled with a second insulation layer pattern. After an insulating interlayer on the substrate including the first and second trenches, a conductive line is formed on a portion of the insulating interlayer where the second trench is positioned so that an inductor is formed over the trench structure.

Abstract: An inductor pattern is formed on a substrate. A conductive pattern having a concave-convex structure is formed on the inductor pattern to increase a surface area of the inductor pattern. An insulation layer is formed on the inductor pattern. After a groove is formed such that the insulation layer is removed to expose the inductor pattern, a conductive pattern is conformally formed on the groove and the insulation layer. Thus, a surface area of the inductor pattern as well as a thickness of an inductor increases to obtain an inductor of a high quality factor.

Abstract: A semiconductor device and a method of fabricating a semiconductor device that includes forming an interlayer insulating film on a semiconductor substrate; depositing a first soft magnetic thin film on the interlayer insulating film through sputtering using a target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; forming a metal film on the first soft magnetic thin film; depositing a second soft magnetic thin film on the metal film through sputtering using the same or another target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; and patterning to form an inductor.

Abstract: An inductor pattern is formed on a substrate. A conductive pattern having a concave-convex structure is formed on the inductor pattern to increase a surface area of the inductor pattern. An insulation layer is formed on the inductor pattern. After a groove is formed such that the insulation layer is removed to expose the inductor pattern, a conductive pattern is conformally formed on the groove and the insulation layer. Thus, a surface area of the inductor pattern as well as a thickness of an inductor increases to obtain an inductor of a high quality factor.

Abstract: A capacitor, a semiconductor device and methods of fabricating the same are disclosed. The capacitor may include a lower electrode, a dielectric layer covering an upper surface of the lower electrode and having a width wider than that of the lower electrode and an upper electrode covering an upper surface and sides of the dielectric layer. The semiconductor device may include a lower insulating layer on a lower line, the capacitor according to example embodiments, the lower electrode on the lower insulating layer and an upper insulating layer on the lower insulating layer and encompassing the capacitor.

Abstract: An inductor pattern is formed on a substrate. A conductive pattern having a concave-convex structure is formed on the inductor pattern to increase a surface area of the inductor pattern. An insulation layer is formed on the inductor pattern. After a groove is formed such that the insulation layer is removed to expose the inductor pattern, a conductive pattern is conformally formed on the groove and the insulation layer. Thus, a surface area of the inductor pattern as well as a thickness of an inductor increases to obtain an inductor of a high quality factor.