Patents by Inventor Joo Ming Too

Joo Ming Too has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock signal networks for structured ASIC devices
    Patent number: 9225335
    Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: December 29, 2015
    Assignee: ALTERA CORPORATION
    Inventors: Chooi Pei Lim, Joo Ming Too, Yew Fatt Kok, Kar Keng Chua
  • CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES
    Publication number: 20140077839
    Abstract: Clock, distribution circuitry for a structured ASIC device includes a deterministic portion, and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served, from that predetermined, location.
    Type: Application
    Filed: November 19, 2013
    Publication date: March 20, 2014
    Applicant: ALTERA CORPORATION
    Inventors: Chooi Pei Lim, Joo Ming Too, Yew Fatt Kok, Kar Keng Chua
  • Clock signal networks for structured ASIC devices
    Patent number: 8595658
    Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: November 26, 2013
    Assignee: Altera Corporation
    Inventors: Chooi Pei Lim, Joo Ming Too, Yew Fatt Kok, Kar Keng Chua
  • Clock duty cycle recovery circuit
    Patent number: 7675336
    Abstract: Circuits, methods, and apparatus that provide the improvement or recovery of a duty cycle of a clock signal. One embodiment of the present invention receives a clock signal that may have a degraded duty cycle. The frequency of the clock signal is divided by two. The frequency-divided signal is delayed in order to generate two signals that are phase shifted from one another by 90 degrees. These signals are then exclusive-ORed together to generate a recovered clock. A control loop is provided to adjust the phase shift between the signals to be approximately 90 degrees.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: March 9, 2010
    Assignee: Altera Corporation
    Inventors: Kok Yoong Foo, Tze Haw Liew, Joo Ming Too
  • CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES
    Publication number: 20080258772
    Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.
    Type: Application
    Filed: June 26, 2008
    Publication date: October 23, 2008
    Applicant: ALTERA CORPORATION
    Inventors: Chooi Pei Lim, Joo Ming Too, Yew Fatt (Edwin) Kok, Kar Keng Chua
  • Clock signal networks for structured ASIC devices
    Patent number: 7404169
    Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: July 22, 2008
    Assignee: Altera Corporation
    Inventors: Chooi Pei Lim, Joo Ming Too, Yew Fatt (Edwin) Kok, Kar Keng Chua