Abstract: An integrated circuit is provided. The integrated circuit includes a plurality of output pads, a plurality of test pads, and a plurality of channel shift switches respectively connected between the plurality of output pads and the plurality of test pads and operated by a plurality of channel shift switch enable signals. A short path between the plurality of output pads may be detected when each of the plurality of channel shift switch enable signals are simultaneously at a high level.

Abstract: A non-volatile memory device includes a plurality of stacked patterns where a tunnel insulation layer, a floating gate, and a dielectric layer are sequentially stacked over a substrate, trenches formed in the substrate between the stacked patterns, an isolation layer gap-filling the trenches and space between the stacked patterns, and a control gate formed over the dielectric layer.

Abstract: A non-volatile memory device includes a plurality of stacked patterns where a tunnel insulation layer, a floating gate, and a dielectric layer are sequentially stacked over a substrate, trenches formed in the substrate between the stacked patterns, an isolation layer gap-filling the trenches and space between the stacked patterns, and a control gate formed over the dielectric layer.

Abstract: An integrated circuit is provided. The integrated circuit includes a plurality of output pads, a plurality of test pads, and a plurality of channel shift switches respectively connected between the plurality of output pads and the plurality of test pads and operated by a plurality of channel shift switch enable signals. A short path between the plurality of output pads may be detected when each of the plurality of channel shift switch enable signals are simultaneously at a high level.

Abstract: A data driver driving a display panel includes a data processing unit receiving digital data synchronously with a master clock signal and storing the digital signal, and a driving signal output unit generating a driving signal corresponding to the digital data in response to a driving instruction signal, and outputting the driving signal to the display panel. The data processing unit is activated at an activation time determined according to a setting signal.

Abstract: The invention relates to a flash memory device and its method of fabrication. The method includes the steps of: forming gate protection patterns over a peripheral region of a semiconductor substrate; forming a tunnel insulating film over the semiconductor substrate; forming a first conductive film over the tunnel insulating film between adjacent gate protection patterns; forming a dielectric film over the first conductive film and the gate protection patterns; etching a portion of the dielectric film in the peripheral region to expose a portion of the first conductive film between adjacent gate protection patterns; forming a second conductive film over the dielectric film and the first conductive film; and etching the second conductive film, the dielectric film, the first conductive film, the tunnel insulating film and the gate protection patterns to form a gate, wherein the gate protection patterns remain on the sidewalls of the first conductive film and the tunnel insulating film in the peripheral region.

Abstract: A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacture process of high-integrated semiconductor devices. It is therefore possible to minimize an interference phenomenon between neighboring cells. Furthermore, an isolation film is etched after a photoresist film covering only a high-voltage transistor region is formed, or a gate oxide film is formed after a semiconductor substrate is etched at a thickness, which is the same as that of the gate oxide film of the high-voltage transistor region, so that a step between the cell region and the high-voltage transistor region is the same. Accordingly, the coupling ratio can be increased even by the gate oxide film of the high-voltage transistor region, which is thicker than the tunnel oxide film of the cell region.

Abstract: A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacturing process of highly integrated semiconductor devices. It is therefore possible to minimize interference between neighboring cells.

Abstract: A method of forming a mask pattern provides a resolution below a resolution of a conventional exposure equipment. The method may include a self-align double etching process in which a nipple formed by hard mask layers having different etching selection ratios is utilized, and a micro pattern to be practically obtained is formed by means of the mask pattern. Using conventional exposure equipment, a micro pattern may have a width below a resolution of the conventional exposure equipment.

Abstract: This patent relates to a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include a semiconductor substrate in which a tunnel insulating layer, and a first conductive layer. At least a portion of the semiconductor substrate is removed to form a trench. A first insulating layer may be formed on an internal surface of the trench. A shield layer may be made of a conductive material is formed on the first insulating layer. A second insulating layer may be formed on the shield layer and is configured to gap fill the trench.

Abstract: The invention relates to a flash memory device and its method of fabrication. The method includes the steps of: forming gate protection patterns over a peripheral region of a semiconductor substrate; forming a tunnel insulating film over the semiconductor substrate; forming a first conductive film over the tunnel insulating film between adjacent gate protection patterns; forming a dielectric film over the first conductive film and the gate protection patterns; etching a portion of the dielectric film in the peripheral region to expose a portion of the first conductive film between adjacent gate protection patterns; forming a second conductive film over the dielectric film and the first conductive film; and etching the second conductive film, the dielectric film the first conductive film, the tunnel insulating film and the gate protection patterns to form a gate, wherein the gate protection patterns remain on the sidewalls of the first conductive film and the tunnel insulating film in the peripheral region.

Abstract: A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacture process of high-integrated semiconductor devices. It is therefore possible to minimize an interference phenomenon between neighboring cells. Furthermore, an isolation film is etched after a photoresist film covering only a high-voltage transistor region is formed, or a gate oxide film is formed after a semiconductor substrate is etched at a thickness, which is the same as that of the gate oxide film of the high-voltage transistor region, so that a step between the cell region and the high-voltage transistor region is the same. Accordingly, the coupling ratio can be increased even by the gate oxide film of the high-voltage transistor region, which is thicker than the tunnel oxide film of the cell region.