Abstract: Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a power-up signal generator configured to generate a power-up signal in response to a memory voltage reaching a target voltage level, an initializer configured to generate an initialization signal in response to the power-up signal and a reset signal and to generate an initial refresh command in response to completion of an initialization operation, and a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, the memory cell array configured to perform an initial refresh operation on the plurality of memory cells in response to the initial refresh command.

Abstract: Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a power-up signal generator configured to generate a power-up signal in response to a memory voltage reaching a target voltage level, an initializer configured to generate an initialization signal in response to the power-up signal and a reset signal and to generate an initial refresh command in response to completion of an initialization operation, and a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, the memory cell array configured to perform an initial refresh operation on the plurality of memory cells in response to the initial refresh command.

Abstract: Provided is a multi-chip system. The multi-chip system includes a plurality of chips and a power sequence controller. The power sequence controller supplies a plurality of external power voltages to the plurality of chips according to a predetermined sequence.