Patents by Inventor Joo Young MOON

Joo Young MOON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10404782
    Abstract: Disclosed are an apparatus and method for reconstructing a transmitted file with high performance in real time, which select analysis target packets for reconstruction by first checking using hardware whether data file-related information is present in packets transmitted via large-capacity traffic over a broadband network, and which reconstruct a file in real time only from the selected analysis target packets. The file reconstruction apparatus for reconstructing a data file from packets on a network includes a packet monitoring unit for extracting packets on the network, a collected packet selection unit for determining whether, for the extracted packets, each packet is a reconstruction target based on flow information, and selecting a reconstruction target packet, and a file reconstruction unit for performing file reconstruction by extracting data from the reconstruction target packet and by storing the extracted data as data of a reconstructed file in a relevant flow.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: September 3, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yang-Seo Choi, Jong-Hyun Kim, Joo-Young Lee, Sun-Oh Choi, Ik-Kyun Kim, Dae-Sung Moon
  • Patent number: 10380045
    Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a semiconductor memory, wherein the semiconductor memory may include: one or more variable resistance elements each exhibiting different resistance states for storing data, wherein each variable resistance element may include: a Magnetic Tunnel Junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a seed layer disposed under the MTJ structure to facilitate a growth of the pinned layer or the free layer; and an amorphous metallic carbon layer disposed under the seed layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 13, 2019
    Assignee: SK hynix Inc.
    Inventor: Joo-Young Moon
  • Publication number: 20190201468
    Abstract: A preparation method of Gynostemma Pentaphyllus leaves extracts with increased amount of small molecular effective saponin and decreased benzopyrene includes the steps of drying fresh Gynostemma Pentaphyllus leaves after heating, treating the dried Gynostemma Pentaphyllus leaves with steam, adding water of 1 to 100-fold volume to the above Gynostemma Pentaphyllus leaves and then preparing a hot water extract by carrying out a hot water extraction at 100-180 V, 0.5-10 atm for 1-120 hours, adding C1-C4 lower alcohol of 1 to 100-fold volume to the residual remained after the hot water extraction and then preparing an alcohol extract of the residual from the hot water extract by carrying out an alcohol extraction at 50-100° C. for 1-4 hours, and mixing the hot water extract and the alcohol extract, and then filtering and concentrating the mixture.
    Type: Application
    Filed: January 4, 2018
    Publication date: July 4, 2019
    Inventors: Tae Young KIM, Joo Myung MOON, Su Hyun KYONG, Yoon Hee KIM
  • Patent number: 10298045
    Abstract: A method of controlling an electronic device is provided which includes electrically connecting a battery with an external power source using a first switch such that a first portion of a first current supplied from the external power source is supplied to a system circuit of the electronic device and a second portion of the first current is supplied to the battery, determining whether a specified condition is satisfied, electrically disconnecting the battery from the external power source using the first switch and electrically connecting the battery with a resistor using a second switch, if the specified condition is satisfied, verifying an electrical characteristic of a current applied to the resistor while the battery is electrically disconnected from the external power source and is electrically connected with the resistor, and determining whether an operation of the battery is abnormal, based at least on a part of the electrical characteristic.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hoon Jung, Joo Hoan Do, Min Woo Song, Sung Won Moon, Hyun Seok Lee, Eui Chan Jung, Moo Young Kim, Hyo Seok Na, Ji Woo Lee
  • Publication number: 20190138467
    Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a semiconductor memory, wherein the semiconductor memory may include: one or more variable resistance elements each exhibiting different resistance states for storing data, wherein each variable resistance element may include: a Magnetic Tunnel Junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a seed layer disposed under the MTJ structure to facilitate a growth of the pinned layer or the free layer; and an amorphous metallic carbon layer disposed under the seed layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventor: Joo-Young Moon
  • Patent number: 10283709
    Abstract: In an embodiment, a substrate that includes a cell region and a dummy region is provided. Lower interconnection structures are formed in the cell region and the dummy region. One or more first multilayered structure patterns are formed in the cell region and one or more second multilayered structure patterns in the dummy region over the lower interconnection structures. The first multilayered structure patterns and second multilayered structure patterns extend in a first direction. Each of the second multilayered structure patterns includes an etch target layer. An insulating material layer is formed over the first multilayered structure patterns and the second multilayered structure patterns. An interlayer insulating layer that fills a space between two adjacent patterns of the first multilayered structure patterns and second multilayered structure patterns is formed by planarizing the insulating material layer. The etch target layer in each of the second multilayered structure patterns is removed.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: May 7, 2019
    Assignee: SK HYNIX INC.
    Inventors: Young Seok Ko, Soo Gil Kim, Joo Young Moon
  • Patent number: 10199272
    Abstract: A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the first direction; a plurality of second contacts alternately arranged between the first contacts and arranged at a predetermined distance in the first direction and the second direction; a plurality of dog bone-type conductive lines connected to the second contacts arranged in the second direction, respectively, among the plurality of second contacts, and having concave parts and convex parts; and a plurality of etching prevention patterns formed over the plurality of conductive lines so as to overlap the conductive lines, respectively.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: February 5, 2019
    Assignee: SK hynix Inc.
    Inventor: Joo-Young Moon
  • Patent number: 10198372
    Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a semiconductor memory, wherein the semiconductor memory may include: one or more variable resistance elements each exhibiting different resistance states for storing data, wherein each variable resistance element may include: a Magnetic Tunnel Junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a seed layer disposed under the MTJ structure to facilitate a growth of the pinned layer or the free layer; and an amorphous metallic carbon layer disposed under the seed layer.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: February 5, 2019
    Assignee: SK hynix Inc.
    Inventor: Joo-Young Moon
  • Publication number: 20180315922
    Abstract: In an embodiment, a substrate that includes a cell region and a dummy region is provided. Lower interconnection structures are formed in the cell region and the dummy region. One or more first multilayered structure patterns are formed in the cell region and one or more second multilayered structure patterns in the dummy region over the lower interconnection structures. The first multilayered structure patterns and second multilayered structure patterns extend in a first direction. Each of the second multilayered structure patterns includes an etch target layer. An insulating material layer is formed over the first multilayered structure patterns and the second multilayered structure patterns. An interlayer insulating layer that fills a space between two adjacent patterns of the first multilayered structure patterns and second multilayered structure patterns is formed by planarizing the insulating material layer. The etch target layer in each of the second multilayered structure patterns is removed.
    Type: Application
    Filed: November 28, 2017
    Publication date: November 1, 2018
    Inventors: Young Seok KO, Soo Gil KIM, Joo Young MOON
  • Publication number: 20180218945
    Abstract: A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the first direction; a plurality of second contacts alternately arranged between the first contacts and arranged at a predetermined distance in the first direction and the second direction; a plurality of dog bone-type conductive lines connected to the second contacts arranged in the second direction, respectively, among the plurality of second contacts, and having concave parts and convex parts; and a plurality of etching prevention patterns formed over the plurality of conductive lines so as to overlap the conductive lines, respectively.
    Type: Application
    Filed: March 29, 2018
    Publication date: August 2, 2018
    Inventor: Joo-Young Moon
  • Patent number: 9935007
    Abstract: A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the first direction; a plurality of second contacts alternately arranged between the first contacts and arranged at a predetermined distance in the first direction and the second direction; a plurality of dog bone-type conductive lines connected to the second contacts arranged in the second direction, respectively, among the plurality of second contacts, and having concave parts and convex parts; and a plurality of etching prevention patterns formed over the plurality of conductive lines so as to overlap the conductive lines, respectively.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: April 3, 2018
    Assignee: SK hynix Inc.
    Inventor: Joo-Young Moon
  • Publication number: 20180040809
    Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a semiconductor memory, wherein the semiconductor memory may include: one or more variable resistance elements each exhibiting different resistance states for storing data, wherein each variable resistance element may include: a Magnetic Tunnel Junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a seed layer disposed under the MTJ structure to facilitate a growth of the pinned layer or the free layer; and an amorphous metallic carbon layer disposed under the seed layer.
    Type: Application
    Filed: April 6, 2017
    Publication date: February 8, 2018
    Inventor: Joo-Young Moon
  • Patent number: 9806652
    Abstract: In some embodiments, a system of controlling an induction electric motor, includes a command voltage output unit for generating a command voltage for operating an inverter according to a command speed and outputting the generated command voltage to the inverter; a control unit for controlling the command voltage output unit such that the command voltage output to the inverter is compared with an operation limiting voltage and the command voltage is corrected to fall within the operation limiting voltage; and the inverter for controlling the induction electric motor depending on the corrected command voltage. Thus, it is possible to precisely control the induction electric motor even in a high speed operation region by regulating the magnitude of the command voltage applied to the induction electric motor by means of dynamic modulation strategies without the magnetic flux controller.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: October 31, 2017
    Assignee: LSIS CO., LTD.
    Inventors: Joo-Young Moon, Hak-Jun Lee, Anno Yoo
  • Publication number: 20170154817
    Abstract: A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the first direction; a plurality of second contacts alternately arranged between the first contacts and arranged at a predetermined distance in the first direction and the second direction; a plurality of dog bone-type conductive lines connected to the second contacts arranged in the second direction, respectively, among the plurality of second contacts, and having concave parts and convex parts; and a plurality of etching prevention patterns formed over the plurality of conductive lines so as to overlap the conductive lines, respectively.
    Type: Application
    Filed: August 15, 2016
    Publication date: June 1, 2017
    Inventor: Joo-Young Moon
  • Publication number: 20160352274
    Abstract: In some embodiments, a system of controlling an induction electric motor, includes a command voltage output unit for generating a command voltage for operating an inverter according to a command speed and outputting the generated command voltage to the inverter; a control unit for controlling the command voltage output unit such that the command voltage output to the inverter is compared with an operation limiting voltage and the command voltage is corrected to fall within the operation limiting voltage; and the inverter for controlling the induction electric motor depending on the corrected command voltage. Thus, it is possible to precisely control the induction electric motor even in a high speed operation region by regulating the magnitude of the command voltage applied to the induction electric motor by means of dynamic modulation strategies without the magnetic flux controller.
    Type: Application
    Filed: May 25, 2016
    Publication date: December 1, 2016
    Inventors: Joo-Young Moon, Hak-Jun Lee, Anno Yoo
  • Patent number: 9330754
    Abstract: A semiconductor memory includes a substrate configured to include a plurality of active regions which are defined by isolation layers extending in a first direction and word lines extending in a second direction intersecting the first direction; source line contacts configured to be alternately disposed over the active regions arranged in the first and second directions and disposed over each of the active regions arranged in a third direction intersecting the first and second directions; source lines configured to extend in the third direction while being coupled to the source line contacts; contacts configured to be disposed over each of the active regions over which the source line contacts are not disposed; variable resistance elements configured to be disposed over each of the contacts; bit line contacts configured to be disposed over each of the variable resistance elements; and bit lines configured to extend in a fourth direction intersecting the first to third directions while being coupled to the bit
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: May 3, 2016
    Assignee: SK hynix Inc.
    Inventor: Joo-Young Moon
  • Publication number: 20160087011
    Abstract: A semiconductor memory includes a substrate configured to include a plurality of active regions which are defined by isolation layers extending in a first direction and word lines extending in a second direction intersecting the first direction; source line contacts configured to be alternately disposed over the active regions arranged in the first and second directions and disposed over each of the active regions arranged in a third direction intersecting the first and second directions; source lines configured to extend in the third direction while being coupled to the source line contacts; contacts configured to be disposed over each of the active regions over which the source line contacts are not disposed; variable resistance elements configured to be disposed over each of the contacts; bit line contacts configured to be disposed over each of the variable resistance elements; and bit lines configured to extend in a fourth direction intersecting the first to third directions while being coupled to the bit
    Type: Application
    Filed: December 7, 2015
    Publication date: March 24, 2016
    Inventor: Joo-Young Moon
  • Patent number: 9208867
    Abstract: A semiconductor memory includes a substrate configured to include a plurality of active regions which are defined by isolation layers extending in a first direction and word lines extending in a second direction intersecting the first direction; source line contacts configured to be alternately disposed over the active regions arranged in the first and second directions and disposed over each of the active regions arranged in a third direction intersecting the first and second directions; source lines configured to extend in the third direction while being coupled to the source line contacts; contacts configured to be disposed over each of the active regions over which the source line contacts are not disposed; variable resistance elements configured to be disposed over each of the contacts; bit line contacts configured to be disposed over each of the variable resistance elements; and bit lines configured to extend in a fourth direction intersecting the first to third directions while being coupled to the bit
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: December 8, 2015
    Assignee: SK hynix Inc.
    Inventor: Joo-Young Moon
  • Publication number: 20140254243
    Abstract: A semiconductor memory includes a substrate configured to include a plurality of active regions which are defined by isolation layers extending in a first direction and word lines extending in a second direction intersecting the first direction; source line contacts configured to be alternately disposed over the active regions arranged in the first and second directions and disposed over each of the active regions arranged in a third direction intersecting the first and second directions; source lines configured to extend in the third direction while being coupled to the source line contacts; contacts configured to be disposed over each of the active regions over which the source line contacts are not disposed; variable resistance elements configured to be disposed over each of the contacts; bit line contacts configured to be disposed over each of the variable resistance elements; and bit lines configured to extend in a fourth direction intersecting the first to third directions while being coupled to the bit
    Type: Application
    Filed: March 5, 2014
    Publication date: September 11, 2014
    Applicant: SK HYNIX INC.
    Inventor: Joo-Young Moon
  • Publication number: 20120241882
    Abstract: A method for fabricating a semiconductor device, the method comprising forming a magnetic tunnel junction pattern on a substrate, forming a spacer having a metal oxide layer on a sidewall of the magnetic tunnel junction pattern, forming a first interlayer insulating layer on the substrate having the spacer and the magnetic tunnel junction pattern formed thereon, forming a first damascene pattern by etching the first interlayer insulating layer so that a top portion of the magnetic tunnel junction pattern is exposed, and forming a first wire buried in the first damascene pattern.
    Type: Application
    Filed: December 23, 2011
    Publication date: September 27, 2012
    Inventor: Joo Young MOON