Abstract: The present disclosure relates to a lithium secondary battery with improved safety during thermal runaway. The lithium secondary battery includes a positive electrode including a positive electrode active material, a negative electrode including a negative electrode active material, and an electrolyte, and has a nominal voltage of 3.68 V or greater, and VP represented by Equation (1) below is 4 mbar·Ah?1·sec?1 or less: Equation (1): VP=?P/(tmax×C).

Abstract: A semiconductor package comprises a package substrate and a first chip stack. The first chip stack includes: a first semiconductor chip on the package substrate, a plurality of second semiconductor chips that are on the first semiconductor chip and have an offset stack structure, and a plurality of first adhesive layers that are respectively on a bottom surface of the first semiconductor chip and bottom surfaces of the second semiconductor chips. The first semiconductor chip includes: a first semiconductor substrate, a plurality of first integrated elements on a top surface of the first semiconductor substrate, and a first wiring layer on the top surface of the first semiconductor substrate. A width of the first semiconductor chip and a width of a lowermost one of the second semiconductor chips are the same. The first semiconductor chip is electrically insulated from the package substrate and the second semiconductor chips.

Abstract: The present disclosure relates to a lithium secondary battery with improved safety during thermal runaway. The lithium secondary battery includes a positive electrode including a positive electrode active material, a negative electrode including a negative electrode active material, and an electrolyte, and has a nominal voltage of 3.68 V or greater, and VP represented by Equation (1) below is 4 mbar·Ah?1·sec?1 or less: Equation (1): VP=?P/(tmax×C).

Abstract: The present disclosure relates to a lithium secondary battery with improved safety during thermal runaway. The lithium secondary battery includes a positive electrode including a positive electrode active material, a negative electrode including a negative electrode active material, and an electrolyte, and has a nominal voltage of 3.68 V or greater, and VT represented by Equation (1) below measured after manufacturing a test module by stacking four of the lithium secondary battery fully charged by being charged to 4.35 V is 4 Ah/sec or less: Equation (1): VT=Ctotal/t.

Abstract: The present disclosure relates to a lithium secondary battery with improved safety during thermal runaway. The lithium secondary battery includes a positive electrode including a positive electrode active material, a negative electrode including a negative electrode active material, and an electrolyte, and has a nominal voltage of 3.68 V or greater, and VT represented by Equation (1) below measured after manufacturing a test module by stacking four of the lithium secondary battery fully charged by being charged to 4.35 V is 4 Ah/sec or less: Equation (1): VT=Ctotal/t.

Abstract: A semiconductor package includes a substrate, a first chip stack on the substrate and including a first semiconductor chip, an underfill pattern on a first side of the first chip stack, and a second chip stack on the first chip stack and including a second semiconductor chip. The second chip stack is stacked so as to be offset to the first chip stack. The first chip stack includes a first adhesive layer under the first semiconductor chip and a first chip protection structure on the first semiconductor chip. The second chip stack includes a second adhesive layer under the second semiconductor chip and a second chip protection structure on the second semiconductor chip. An extension portion of the second adhesive layer is on one side of the first chip protection structure, and the underfill pattern extends from the first side of the first chip stack to the extension portion.

Abstract: A semiconductor device includes a semiconductor substrate including a device region and an edge region; a semiconductor component on the device region; a metal structure on the edge region; an insulating layer surrounding the semiconductor component and the metal structure; and a pad on the semiconductor component, wherein the metal structure is surrounded by the insulating layer and is not exposed at a side surface of the insulating layer, and wherein the metal structure is electrically insulated from the semiconductor component.

Abstract: The present invention provides an apparatus for managing atopic dermatitis based on a learning model and a method therefor.

Abstract: A display module includes a display panel having a plurality of pixels and a display driver configured to drive a partial portion of the plurality of pixels that are positioned in an alignment mark area to display an alignment mark in the alignment mark area. A stereoscopic lens including a base is disposed on the display module. A plurality of lenses is disposed on the base and includes at least one flat portion surrounded by the plurality of lenses and overlapping the alignment mark area.

Abstract: The present disclosure provides a delirium risk predicting method which includes receiving at least one of blood data, severity evaluation data, mental state evaluation data, and bio signal data, medication data, and medical treatment data, for an subject, predicting a delirium risk for the subject, using a delirium risk prediction model configured to predict a delirium risk, based on at least one data, the medication data, and the medical treatment data, and providing the delirium risk predicted for the subject. The at least one data, the medication data, and the medical treatment data are defined as initial data which is evaluated or measured only once for the subject and a delirium risk predicting device using the same.

Abstract: A display module includes a display panel having a plurality of pixels and a display driver configured to drive a partial portion of the plurality of pixels that are positioned in an alignment mark area to display an alignment mark in the alignment mark area. A stereoscopic lens including a base is disposed on the display module. A plurality of lenses is disposed on the base and includes at least one flat portion surrounded by the plurality of lenses and overlapping the alignment mark area.

Abstract: A passivation structure may include a first passivation pattern on an upper surface of a semiconductor chip provided on a semiconductor substrate, and a second passivation pattern arranged on a scribe lane of the semiconductor substrate adjacent to the semiconductor chip. The second passivation pattern is spaced apart from the first passivation pattern to form a crack-blocking groove between the second passivation pattern and the first passivation pattern.

Abstract: The present disclosure provides a delirium risk predicting method which includes receiving at least one of blood data, severity evaluation data, mental state evaluation data, and bio signal data, medication data, and medical treatment data, for an subject, predicting a delirium risk for the subject, using a delirium risk prediction model configured to predict a delirium risk, based on at least one data, the medication data, and the medical treatment data, and providing the delirium risk predicted for the subject. The at least one data, the medication data, and the medical treatment data are defined as initial data which is evaluated or measured only once for the subject and a delirium risk predicting device using the same.

Abstract: A passivation structure may include a first passivation pattern on an upper surface of a semiconductor chip provided on a semiconductor substrate, and a second passivation pattern arranged on a scribe lane of the semiconductor substrate adjacent to the semiconductor chip. The second passivation pattern is spaced apart from the first passivation pattern to form a crack-blocking groove between the second passivation pattern and the first passivation pattern.

Abstract: A radiography guide system includes a patient image providing unit for providing, on a screen, one piece of information among information on the position where a virtual patient is to be placed, a radiographic direction, and a radiographic angle, and a patient image which represents, as a three-dimensional image, the virtual patient's posture corresponding to a viewing angle, and an overlay image providing unit for generating an external image which represents, as a three-dimensional image, the appearance of the virtual patient's body according to the position information, the radiographic direction, and the radiographic angle, an internal image which represents the skeleton structure of the body as a three-dimensional image, and a radiographic image of the body. The overlay image providing unit provides, on the screen, an overlay image which overlappingly represents the internal image, the external image, and the radiographic image in the state where the images are registered.

Abstract: A radiography guide system includes a patient image providing unit for providing, on a screen, one piece of information among information on the position where a virtual patient is to be placed, a radiographic direction, and a radiographic angle, and a patient image which represents, as a three-dimensional image, the virtual patient's posture corresponding to a viewing angle, and an overlay image providing unit for generating an external image which represents, as a three-dimensional image, the appearance of the virtual patient's body according to the position information, the radiographic direction, and the radiographic angle, an internal image which represents the skeleton structure of the body as a three-dimensional image, and a radiographic image of the body. The overlay image providing unit provides, on the screen, an overlay image which overlappingly represents the internal image, the external image, and the radiographic image in the state where the images are registered.

Abstract: An apparatus and a method for testing drilling efficiency of a drill bit, according to the present invention, calculate an amount of fractured rock according to a button arrangement, thereby obtaining an optimum button arrangement.

Abstract: A drill bit including a button array having different radii extending from the center of a head section, and more particularly, to a drill bit in which buttons are arranged so as to have different radii from the center of a drill bit head section, thereby striking bedrock points having different radii and improving the efficiency of a drilling operation.

Abstract: A semiconductor package includes a substrate, and a first semiconductor chip stack disposed on the substrate. The first semiconductor chip stack includes a plurality of first semiconductor chips. The first semiconductor chips are stacked in a staircase configuration along a first direction. A first support is disposed on the substrate. The first support is spaced apart from the first semiconductor chip stack. A second semiconductor chip stack is disposed on the first semiconductor chip stack and the first support. The second semiconductor chip stack includes a plurality of second semiconductor chips. The second semiconductor chips are stacked in a second staircase configuration along a second direction opposite the first direction. A height of the first semiconductor chip stack is substantially equal to a height of the first support.

Abstract: A semiconductor package includes a substrate, and a first semiconductor chip stack disposed on the substrate. The first semiconductor chip stack includes a plurality of first semiconductor chips. The first semiconductor chips are stacked in a staircase configuration along a first direction. A first support is disposed on the substrate. The first support is spaced apart from the first semiconductor chip stack. A second semiconductor chip stack is disposed on the first semiconductor chip stack and the first support. The second semiconductor chip stack includes a plurality of second semiconductor chips. The second semiconductor chips are stacked in a second staircase configuration along a second direction opposite the first direction. A height of the first semiconductor chip stack is substantially equal to a height of the first support.