Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

Abstract: Disclosed is a preparation method of manufacturing a thermoelectric nanowire having a core/shell structure. The preparation method of thermoelectric nanowire includes preparing a substrate provided with an oxide layer formed thereon, and forming a Bi thin film on the oxide layer, heat treating a structure produced during forming the Bi thin film to induce compressive stress due to differences in coefficients of thermal expansion between the substrate, the oxide layer and the Bi thin film, to grow a Bi single crystal nanowire on the Bi thin film, and cooling the substrate of a structure on which the nanowire is grown to a low temperature, and sputtering a thermoelectric material on the Bi single crystal nanowire in a cooled state to manufacture a thermoelectric nanowire having a core/shell structure of Bi/thermoelectric material.