Abstract: A display device includes: a plurality of pixels; a first pixel unit comprising a first portion of the plurality of pixels; a second pixel unit comprising a second portion of the plurality of pixels; and a data driver configured to supply a data voltage to the first pixel unit and the second pixel unit, wherein the data driver is configured to generate a data voltage to be supplied to the first pixel unit based on different gamma voltages even when the same grayscale is expressed according to a driving method, and the second pixel unit is configured to be driven or not driven according to the driving method.

Abstract: A display device includes a display panel, a scan driver, a data driver, a sensing circuit, and a controller configured to select a pixel row from a plurality of pixel rows in a vertical blank period of each frame period. The vertical blank period includes a sensing time in which the sensing circuit performs a sensing operation for the selected pixel row. The sensing circuit measures a first source voltage of a driving transistor of each pixel in the selected pixel row at a first time point of the sensing time, and measures a second source voltage of the driving transistor at a second time point of the sensing time. The controller predicts a current saturated source voltage of the driving transistor based on the first and second source voltages, and determines a threshold voltage change amount of the driving transistor based on a difference between a previous saturated source voltage and the current saturated source voltage.

Abstract: A light emission driving circuit includes a driving circuit configured to output a light emission driving signal to a first output terminal and output a switching signal to a first node in response to clock signals and a first carry signal, and a first masking circuit configured to output a second carry signal to a second output terminal in response to a masking clock signal, the light emission driving signal, and the switching signal. The masking clock signal is a signal which is maintained at a first level during a normal mode and periodically changes during a low power mode.

Abstract: A display apparatus includes a display panel, a driving controller and a data driver. The driving controller is configured to predict a panel temperature according to a position in the display panel based on input image data, to calculate a block current of a display block of the display panel and a panel resistance according to the position in the display panel based on the panel temperature, to calculate a voltage drop according to the position in the display panel based on the block current and the panel resistance and to compensate the input image data based on the voltage drop to generate a data signal. The data driver is configured to convert the data signal to a data voltage and to output the data voltage to the display panel.

Abstract: A display device includes display panels, a data converter that renders input image data to convert the input image data corresponding to edge regions of the display panels adjacent to a boundary portion between the display panels into correction data, and a driving controller that receives the correction data and generates a control signal that drives the display panels based on the correction data. The data converter generates the correction data in which an image displayed in the edge region is shifted based on a difference between values of the input image data corresponding to the edge regions of the display panels adjacent to the boundary portion between the display panels adjacent to each other.

Abstract: A data driver includes a digital to analog converter, a buffer and a buffer controller. The digital to analog converter is configured to receive a data signal having a digital type and to convert the data signal into a data voltage having an analog type. The buffer is configured to buffer the data voltage and to output the data voltage. The buffer controller is configured to determine a parameter of the buffer based on previous line data of the data signal and present line data of the data signal.

Abstract: A display device includes: a plurality of pixels, where each of the pixels includes a light emitting device and a pixel circuit coupled to the light emitting device; a scan driver which supplies a scan signal to the pixel circuit; a data driver which supplies a data signal to the pixel circuit; a power supply which supplies a voltage to the pixel circuit; a timing controller which controls the scan driver; a first signal generator which provides a first clock signal to the timing controller; and a second signal generator which provides a second clock signal to the timing controller.

Abstract: A display device includes a display panel including a first partial panel region and a second partial panel region, and a panel driver configured to drive the display panel. The panel driver determines a first driving frequency for the first partial panel region and a second driving frequency for the second partial panel region. When the first driving frequency and the second driving frequency are different from each other, the panel driver sets a boundary portion including a boundary between the first partial panel region and the second partial panel region, and determines a third driving frequency for the boundary portion to be between the first driving frequency and the second driving frequency.

Abstract: A pixel circuit includes a main-circuit that controls an organic light-emitting element by controlling a driving current to flow into the organic light-emitting element and a sub-circuit including a first compensation transistor including a gate terminal which receives a first gate signal, a second compensation transistor including a gate terminal which receives a second gate signal, and an initialization transistor including a gate terminal which receives an initialization signal. Here, in a low-frequency driving mode, a driving frequency of the first gate signal is N hertz (Hz), a driving frequency of the initialization signal is N Hz, a driving frequency of the second gate signal is M Hz, the first compensation transistor and the initialization transistor are turned on during a first time duration in N non-light-emitting periods per second, and the second compensation transistor is turned on during a second time duration in M non-light-emitting periods per second.

Abstract: A display device according to some embodiments includes pixels divided into pixel rows arranged in a horizontal direction, and including a light emitting element, and a first transistor for applying a drive current to the light emitting element, and a sensing driver configured to receive a sensing value extracted from one or more of the pixels, wherein at least one pixel row of the pixel rows is configured to be driven in one frame including an emission period in which the light emitting element emits light after a data voltage is applied to the pixels, and an active sensing period for sensing a characteristic of the first transistor.

Abstract: A display apparatus includes a display panel and a timing controller. The timing controller generates first output image data based on input image data and sets a driving frequency of the display panel as a first frequency in a first operation mode. The timing controller converts the input image data into second output image data and sets the driving frequency of the display panel as a second frequency lower than the first frequency in a second operation mode. The display panel displays a first image based on the first frequency and the first output image data in the first operation mode. The first image is represented by X grayscales. The display panel displays a second image based on the second frequency and the second output image data in the second operation mode. The second image is represented by Y grayscales, where Y is less than X.

Abstract: A display device includes pixels, and first, second, and third gate lines and data lines connected to the pixels. At least one of the pixels includes a light emitting element, a first transistor connected between a first power source and the light emitting element for driving the light emitting element according to a voltage of a first node, a second transistor connected between the first node and a corresponding data line, and driven according to a voltage of a corresponding first gate line, a capacitor connected between the first node and a second node between the first transistor and the light emitting element, a third transistor between the second node and an initialization power line, and driven according to a voltage of a corresponding second gate line, and a fourth transistor connected between the first and second nodes, and driven according to a voltage of a corresponding third gate line.

Abstract: A data driver includes a multi-channel sample/hold circuit electrically connected between a digital-to-analog converter and a data buffer. The multi-channel sample/hold circuit includes a first sample/hold circuit connected to a first channel and a second sample/hold circuit connected to a second channel. The first sample/hold circuit performs a first drive operation and a second drive operation. The first drive operation includes sampling a data voltage as a buffer input voltage and maintaining the buffer input voltage during an nth horizontal time. The second drive operation includes outputting the buffer input voltage to an output terminal of the buffer during an (n+1)th horizontal time. The second sample/hold circuit performs the second drive operation during the nth horizontal time and performs the first drive operation during the (n+1)th horizontal time.

Abstract: A digital-to-analog converter (“DAC”) converts digital image data into analog image signals. The DAC includes a stage outputting different voltages to a first output terminal and a second output terminal based on a voltage supplied to a first input terminal, a voltage supplied to a second input terminal, and a first input bit. The stage includes a switch circuit including switches that are alternately turned on by a control signal, and outputting an intermediate output voltage to a third output terminal based on a first input voltage supplied to the first input terminal and a second input voltage supplied to the second input terminal, and a selector outputting one of the first input voltage and the second input voltage, and the intermediate output voltage.

Abstract: A light emission driving circuit includes a driving circuit configured to output a light emission driving signal to a first output terminal and output a switching signal to a first node in response to clock signals and a first carry signal, and a first masking circuit configured to output a second carry signal to a second output terminal in response to a masking clock signal, the light emission driving signal, and the first switching signal. The masking clock signal is a signal which is maintained at a first level during a normal mode and periodically changes during a low power mode.

Abstract: A display device includes: a first partial emission driver configured to provide first emission control signals to a first partial panel area of the display panel, and a second partial emission driver configured to provide second emission control signals to a second partial panel area of the display panel; and a power management block configured to: provide a first voltage and a second voltage to the emission driver, in response to the first partial emission driver generating the first emission control signals; and provide a third voltage and a fourth voltage to the emission driver in response to the second partial emission driver generating the second emission control signals; and an emission control block configured to receive the first voltage and the second voltage from the power management block and to provide a first clock signal and a second clock signal to the emission driver.

Abstract: A scan driving circuit includes: a driving circuit configured to output a scan signal to an output terminal in response to clock signals and a carry signal; and a masking circuit configured to stop the driving circuit from outputting the scan signal in response to a masking signal and a signal indicating an operating state of the driving circuit.

Abstract: A data driver includes a gamma voltage generator configured to generate gamma voltages based on a number of data bits of a pixel data; a first digital-to-analog block configured to generate a plurality of time-division gamma voltage signals respectively corresponding to a plurality of gamma voltage groups; a plurality of time-division gamma voltage line groups for transferring the plurality of time-division gamma voltage signals; a second digital-to-analog block configured to select a time-division gamma voltage signal among the time-division gamma voltage signals according to upper bits of the pixel data in each channel; a time-division gamma voltage select block configured to select a gamma voltage according to lower bits of the pixel data in each channel; and an output buffer block configured to output the selected gamma voltage in each channel.

Abstract: A digital-to-analog converter (“DAC”) converts digital image data into analog image signals. The DAC includes a stage outputting different voltages to a first output terminal and a second output terminal based on a voltage supplied to a first input terminal, a voltage supplied to a second input terminal, and a first input bit. The stage includes a switch circuit including switches that are alternately turned on by a control signal, and outputting an intermediate output voltage to a third output terminal based on a first input voltage supplied to the first input terminal and a second input voltage supplied to the second input terminal, and a selector outputting one of the first input voltage and the second input voltage, and the intermediate output voltage.

Abstract: A display apparatus includes a display panel, a data driver, and a power voltage generator. The display panel includes a plurality of pixels and configured to display an image. The data driver is configured to apply a data voltage to the display panel. The power voltage generator is configured to provide a power voltage and an initialization voltage to the display panel. The power voltage generator is configured to receive a feedback initialization voltage from the display panel and configured to compensate the initialization voltage based on the feedback initialization voltage.