Abstract: A semiconductor device includes a first structure including a memory region and a first peripheral circuit region; and a second structure overlapping the first structure vertically and including a core circuit region and a second peripheral circuit region, wherein the memory region includes a first cell vertical active pattern; a first word line having a side surface facing a first side surface of the first cell vertical active pattern; and a first cell gate dielectric layer between the first cell vertical active pattern and the first word line, wherein the first peripheral circuit region includes a first peripheral vertical active pattern disposed at substantially the same level as the first cell vertical active pattern; a first peripheral gate electrode having a side surface facing a first side surface of the first peripheral vertical active pattern; and a first peripheral gate dielectric layer between the first peripheral vertical active pattern and the first peripheral gate electrode.

Abstract: A semiconductor memory device includes a first structure on a substrate and including core regions and a first peripheral circuit region, and a second structure on the first structure and including cell array regions and a second peripheral circuit region. The second structure includes a first active pattern in each of the cell array regions and perpendicular to an upper surface of the first structure, a word line adjacent to one side of the first active pattern and extending in a first direction parallel to the upper surface of the first structure, a bit line in contact with a lower surface of the first active pattern and extending in a second direction intersecting the first direction, a second active pattern in the second peripheral circuit region and perpendicular to the upper surface of the first structure, and an anti-fuse gate electrode on one side of the second active pattern.

Abstract: A semiconductor device may include a substrate including an insulating substrate. A semiconductor layer is on the substrate. An active pattern is on the semiconductor layer. A bit line is disposed in the insulating substrate. The bit line extends along a first direction parallel to a bottom surface of the substrate. A buried node contact penetrates the semiconductor layer in a direction perpendicular to the bottom surface of the substrate. A word line penetrates the active pattern in a second direction that is parallel to the bottom surface of the substrate and crosses the first direction. The active pattern may be connected to the bit line through the buried node contact. A top surface of the buried node contact may be higher than a bottom surface of the active pattern.

Abstract: A semiconductor device includes a first active pattern included in an upper portion of a substrate in a memory cell region, and having an isolated shape extending so that a direction oblique to a first direction is a major axis direction of the first active pattern. A first device isolation pattern provided inside a first trench included in the substrate, and covering a side wall of the first active pattern is provided. A first gate structure is provided inside a gate trench extending in the first direction on upper portions of the first active pattern and the first device isolation pattern. A barrier impurity region is selectively formed only on surfaces of both side walls of a major axis of the first active pattern. First and second impurity regions are provided on the upper portion of the first active pattern adjacent to both sides of the first gate structure.

Abstract: An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.

Abstract: An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.

Abstract: Provided are a multi-direction channel transistor having a gate having an increased effective width and a multi-direction channel, and a semiconductor device including the multi-direction channel transistor, wherein the multi-direction channel transistor includes at least one fin on an active region on a substrate and disposed adjacent to a recess extending in a first direction; a gate line extending in a second direction crossing the first direction and covering at least a portion of the at least one fin and the recess; source/drain regions on the active region at both sides of the gate line; and a channel region in the active region under the gate line between the source/drain regions, wherein the first direction is diagonal to the second direction, and a dielectric film under the gate line has substantially the same thickness on both the at least one fin and the recess.

Abstract: Provided are a multi-direction channel transistor having a gate having an increased effective width and a multi-direction channel, and a semiconductor device including the multi-direction channel transistor, wherein the multi-direction channel transistor includes at least one fin on an active region on a substrate and disposed adjacent to a recess extending in a first direction; a gate line extending in a second direction crossing the first direction and covering at least a portion of the at least one fin and the recess; source/drain regions on the active region at both sides of the gate line; and a channel region in the active region under the gate line between the source/drain regions, wherein the first direction is diagonal to the second direction, and a dielectric film under the gate line has substantially the same thickness on both the at least one fin and the recess.

Abstract: A crosslinkable low density polyethylene blend composition, cured product made therefrom, methods of making and using same, and articles containing same.

Abstract: A system for controlling voltage unbalance in a direct current distribution system includes a measurement processor configured to measure a positive load current, and a negative load current at a first load point, including a first load connected to a positive line and a neutral line and a second load connected to the neutral line and a negative line, and at a second load point in a power distribution system; and a control processor configured to determine whether to activate a first load point switching signal based on the positive and negative load currents at the first and second load points to control the first load point to switch the connections of the first load and the second load between the positive line and the negative line.

Abstract: A semiconductor memory device includes a bit line sense amplifier, a first column select gate, and a second column select gate. The bit line sense amplifier senses an electric potential difference between a bit line and a complementary bit line during a sensing operation for memory cells. The first column select gate transfers an electric potential on the bit line to a local sense amplifier based on a column select signal. The second column select gate transfers an electric potential on the complementary bit line to the local sense amplifier based on the column select signal. The first and second column select gates have different current drive abilities to compensate a difference in bit line interconnection resistance.

Abstract: A system for controlling voltage unbalance in a direct current distribution system includes a measurement processor configured to measure a positive load current, and a negative load current at a first load point, including a first load connected to a positive line and a neutral line and a second load connected to the neutral line and a negative line, and at a second load point in a power distribution system; and a control processor configured to determine whether to activate a first load point switching signal based on the positive and negative load currents at the first and second load points to control the first load point to switch the connections of the first load and the second load between the positive line and the negative line.

Abstract: A semiconductor device includes a semiconductor substrate having a first transistor region and a second transistor region, a first MOSFET including a first gate insulating layer structure and a first gate electrode structure, and a second MOSFET including a group IV compound semiconductor layer, a second gate insulating layer structure, and a second gate electrode structure. The first gate insulating layer structure and the first gate electrode structure are disposed on the first transistor region of the semiconductor substrate. The group IV compound semiconductor layer is disposed on the second transistor region of the semiconductor substrate, and the second gate insulating layer and the second gate electrode structure are disposed on the group IV compound semiconductor layer. Each of the first and second gate insulating layer structures includes a high-k dielectric (insulating) layer.

Abstract: A semiconductor memory device includes a bit line sense amplifier, a first column select gate, and a second column select gate. The bit line sense amplifier senses an electric potential difference between a bit line and a complementary bit line during a sensing operation for memory cells. The first column select gate transfers an electric potential on the bit line to a local sense amplifier based on a column select signal. The second column select gate transfers an electric potential on the complementary bit line to the local sense amplifier based on the column select signal. The first and second column select gates have different current drive abilities to compensate a difference in bit line interconnection resistance.

Abstract: There is provided a semiconductor device. The semiconductor device may include multiple contacts plugs, an insulation layer pattern, a metal oxide layer pattern, a metal pattern and a metal line. The contact plugs contact a substrate. The insulation layer pattern is formed between the contact plugs and has a top surface lower than those of the contact plugs. The metal oxide layer pattern is formed on the insulation layer pattern, and has a dielectric constant higher than that of silicon oxide. The metal pattern is formed on the metal oxide layer pattern and contacts sidewalls of the contact plugs. The metal line contacts top surfaces of the contact plugs and the metal pattern and extends thereon.

Abstract: There is provided a semiconductor device. The semiconductor device may include multiple contacts plugs, an insulation layer pattern, a metal oxide layer pattern, a metal pattern and a metal line. The contact plugs contact a substrate. The insulation layer pattern is formed between the contact plugs and has a top surface lower than those of the contact plugs. The metal oxide layer pattern is formed on the insulation layer pattern, and has a dielectric constant higher than that of silicon oxide. The metal pattern is formed on the metal oxide layer pattern and contacts sidewalls of the contact plugs. The metal line contacts top surfaces of the contact plugs and the metal pattern and extends thereon.

Abstract: A semiconductor integrated circuit device having a 6F2 layout is provided. The semiconductor integrated circuit device includes a substrate; a plurality of unit active regions disposed in the substrate and extending in a first direction; first and second access transistors including first and second gate lines disposed on the substrate and extending across the unit active regions in a second direction forming an acute angle with the first direction; a first junction area disposed in the substrate between the first and second gate lines and second junction areas disposed on sides of the first and second gate lines where the first junction area is not disposed; a plurality of bitlines disposed on the substrate and extending in a third direction forming an acute angle with the first direction; and a plurality of bitline contacts directly connecting the first junction area and the bitlines.

Abstract: A semiconductor integrated circuit device having a 6F2 layout is provided. The semiconductor integrated circuit device includes a substrate; a plurality of unit active regions disposed in the substrate and extending in a first direction; first and second access transistors including first and second gate lines disposed on the substrate and extending across the unit active regions in a second direction forming an acute angle with the first direction; a first junction area disposed in the substrate between the first and second gate lines and second junction areas disposed on sides of the first and second gate lines where the first junction area is not disposed; a plurality of bitlines disposed on the substrate and extending in a third direction forming an acute angle with the first direction; and a plurality of bitline contacts directly connecting the first junction area and the bitlines.

Abstract: The present invention relates to a ?-[2-(polyalkyleneoxy)ethylthio]alkylalkoxysilane derivative and a preparation method thereof, more particularly to a ?-[2-(polyalkyleneoxy)ethylthio]alkylalkoxysilane derivative prepared by transforming a (?-mercaptoalkyl)alkylalkoxysilane compound into a ?-(alkoxysilyl)alkylthiolate metal salt by treating it with a metallic base and performing dehalometallation at low reaction temperature using a poly(alkyleneoxy)alkyl ether halide or a poly(alkyleneoxy)bis(haloalkyl) ether to form a carbon-sulfur bond and a preparation method thereof. The novel compound of the present invention has not only a Si—OR bond but also contains a sulfur atom in the molecule, so that it can be used as monomer for synthesizing hydrophilic functional silicon polymers, source material of silicon-based surfactants and surface modifier of organic/inorganic materials.

Abstract: This invention relates to (organothiomethyl)chlorosilanes and methods for their preparation by the dehydrohalogenative Si—C coupling reaction of oranothiomethyl halides with Si—H containing chlorosilanes (hydrosilanes), wherein a mixture of oranothiomethyl halide and hydrosilane is heated in the presence of tertiary amine or organic salts (quaternary organoammonium and organophosphonium halides to give (organothiomethyl)chlorosilanes, which is existing a sulfur atom in alkyl chain, (formula:: R2SCH2SiCl2R1) in good yield, wherein R1 represents a hydrogen atom, halogen, or C1-C6 alkyl; R2 is selected from the group consisting of C1-C6 alkyl or an aryl group. Especially, this reaction using organic salt as a catalyst provide better economical matter and yield compared with conventional methods, because only catalytic amount of organic salt is required and the catalyst can be separated from the reaction mixture and recycled easily.