Abstract: A pixel includes a light-emitting element, a first transistor connected between a first voltage line and the light-emitting element, a second transistor connected between the first voltage line and the first transistor, a third transistor connected between the first transistor and the light-emitting element, and a fourth transistor connected between the light-emitting element and a second voltage line, wherein the pixel is configured to emit light in a plurality of emission periods between a plurality of non-emission periods during one frame, and the second transistor is turned off and the third transistor is turned on in even-numbered non-emission periods among the plurality of non-emission periods.

Abstract: A display device includes: a memory, a driving controller, a light emitting element, a first transistor including a first electrode, a second electrode, and a gate electrode for receiving a data signal, a second transistor connected between a first driving voltage line and the first electrode of the first transistor and receiving a first emission signal, and a third transistor connected between the second electrode of the first transistor and the light emitting element and receiving a second emission signal. The first emission signal includes a compensation period and an emission period, and the memory stores instructions that, when executed by the driving controller, cause the driving controller to determine a compensation time of the compensation period depending on target luminance.

Abstract: A pixel of a display device includes a first transistor including a gate connected to a first node, a first terminal, and a second terminal connected to a second node, a first storage capacitor connected between the first node and the second node, a second storage capacitor connected between the first node and the second node, a second transistor including a gate connected to the first node, a first terminal, and a second terminal connected to the first node, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor including a gate receiving an emission signal, a first terminal connected to a line of a first power supply voltage, and a second terminal connected to the first terminal of the first transistor, and a light emitting element including an anode connected to the second node, and a cathode connected to a line of a second power supply voltage.

Abstract: The invention disclosed herein relates to methods for reducing aggregation of bispecific antibodies, for example reducing aggregation of bispecific T cell engager (BiTE) antibody constructs, resulting from storage under frozen conditions by holding the antibodies at certain temperatures after thaw.

Abstract: One or more embodiments provide a light-emitting display device including a substrate, a first transistor including a lower electrode above the substrate, a first semiconductor overlapping the lower electrode, and a first gate electrode overlapping the first semiconductor, a light-emitting diode electrically connected to the first transistor, a storage capacitor including a first storage electrode electrically connected to the lower electrode, and a second storage electrode overlapping the first storage electrode, a shielding electrode at a same layer as the lower electrode or as the first semiconductor, a data line overlapping the shielding electrode, and configured to transmit a data voltage, and an auxiliary electrode between the shielding electrode and the data line, overlapping the shielding electrode, and adjacent to the first gate electrode.

Abstract: A pixel of a display device includes a first transistor including a gate connected to a first node, a first terminal, and a second terminal connected to a second node, a first storage capacitor connected between the first node and the second node, a second storage capacitor connected between the first node and the second node, a second transistor including a gate connected to the first node, a first terminal, and a second terminal connected to the first node, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor including a gate receiving an emission signal, a first terminal connected to a line of a first power supply voltage, and a second terminal connected to the first terminal of the first transistor, and a light emitting element including an anode connected to the second node, and a cathode connected to a line of a second power supply voltage.

Abstract: A display device that includes multiple pixels, each pixel includes a light emitting element, a multiple of transistors, multiple voltage sources and capacitors. The pixel circuit is designed and the pixels are driven so that a driving current going through the light emitting element is independent of a threshold voltage of a driving transistor of the multiple transistors. As a result, luminance variation due to threshold voltage can be minimized, and residual image can be reduced.

Abstract: A display device includes: a first metal layer on a substrate; an active layer on the first metal layer; a second metal layer on the active layer; a third metal layer on the second metal layer; a first transistor including: a semiconductor region at the active layer; a drain electrode on a first side of the semiconductor region; a source electrode on a second side of the semiconductor region; and a gate electrode at the second metal layer; a first capacitor including: a first capacitor electrode at the first metal layer, and electrically connected to the gate electrode of the first transistor; and a second capacitor electrode integral with the source electrode of the first transistor, and on a third side of the semiconductor region of the first transistor; and a compensation pattern at the active layer, and on a fourth side of the semiconductor region of the first transistor.

Abstract: The present invention provides an improved pharmaceutical composition for storage and administration comprising (a) a bispecific antibody construct comprising a first domain binding to a target cell surface antigen and a second domain binding to a second antigen, wherein the bispecific antibody construct is present at a concentration in the range from about 0.5 ?g/ml to 20 mg/ml, (b) a preservative at a concentration effective to inhibit the growth of microbes, and (c) a diluent wherein bispecific antibody construct is stable and recoverable.

Abstract: The disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a 4th generation (4G) communication system such as long term evolution (LTE). An electronic device including an antenna in a wireless communication system is provided. The electronic device includes a radiator, a body, and a feeding circuit for transmitting a signal, wherein the radiator is coupled to at least a part of the body, the feeding circuit is coupled to the body to support the body, and the radiator is disposed to be spaced apart from the feeding circuit to form an air gap.

Abstract: A pixel and a display device including the pixel are disclosed. The pixel comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a light emitting element. The eighth transistor includes a gate electrode configured to receive a second data voltage, a first electrode connected to a fourth node, and a second electrode configured to receive an initialization voltage. The eighth transistor adjusts a voltage level of the first capacitor based on a difference between the voltage level of the first capacitor and a level of the second data voltage.

Abstract: A pixel and a display device including the pixel are disclosed. The pixel comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a light emitting element. The eighth transistor includes a gate electrode configured to receive a second data voltage, a first electrode connected to a fourth node, and a second electrode configured to receive an initialization voltage. The eighth transistor adjusts a voltage level of the first capacitor based on a difference between the voltage level of the first capacitor and a level of the second data voltage.

Abstract: The present disclosure provides a low pH pharmaceutical composition comprising (a) an antibody constructs comprising a first domain binding to a target cell surface antigen, a second domain binding to a second antigen and preferably a third domain, which is a specific Fc modality, (b) at least one buffer agent, (c) at least one saccharide, and (d) at least one surfactant; and wherein the pH of the pharmaceutical composition is in the range of 3.5 to 6.

Abstract: The present invention provides an improved pharmaceutical composition for storage and administration comprising (a) a bispecific antibody construct comprising a first domain binding to a target cell surface antigen and a second domain binding to a second antigen, wherein the bispecific antibody construct is present at a concentration in the range from about 0.5 ?g/ml to 20 mg/ml, (b) a preservative at a concentration effective to inhibit the growth of microbes, and (c) a diluent wherein bispecific antibody construct is stable and recoverable.

Abstract: An optical cable terminal box for distributing an optical cable with a plurality of cores to subscriber lines is provided. The optical cable terminal box may include a housing having a slot, the slot having a first receiving groove formed at an edge of the slot. The optical cable terminal box may also include a cover member coupled to the housing to close the slot, and the cover member may have a second receiving groove formed at an edge of the cover member. When the cover member closes the slot, the first and second grooves may be coupled to each other to form a wiring hole that is configured to pass an optical cable therethrough.

Abstract: An optical cable terminal box for distributing an optical cable with a plurality of cores to subscriber lines is provided. The optical cable terminal box may include a housing having a slot, the slot having a first receiving groove formed at an edge of the slot. The optical cable terminal box may also include a cover member coupled to the housing to close the slot, and the cover member may have a second receiving groove formed at an edge of the cover member. When the cover member closes the slot, the first and second grooves may be coupled to each other to form a wiring hole that is configured to pass an optical cable therethrough.