Abstract: Provided are a device and method for updating a register transfer level (RTL) power model for power consumption analysis of a semiconductor circuit by at least one processor. The method includes receiving a test scenario including a plurality of time slots, inputting the test scenario to an initial power model and identifying a first set of time slots related to a power state which is not defined by the initial power model among the plurality of time slots, determining a power value for a specific power state related to a second set of time slots which is a subset of the first set of time slots, and updating the initial power model on the basis of the specific power state and the determined power value. Each of the plurality of time slots is related to one power state.

Abstract: Example embodiments relate to a method for designing integrated circuit based on a computer program including at least one instruction performed by an integrated circuit design system including a processor, the method comprising mapping, by the processor, at least one netlist signal to at least one RTL signal, determining, by the processor, a target netlist signal among the at least one netlist signal, determining, by the processor, a target expression of the target netlist signal using the netlist signal mapped to the at least one RTL signal based on at least a part of the netlist circuit, simulating, by the processor, on the at least one RTL signal, calculating, by the processor, signal simulation predicting information for the target netlist signal using the target expression and generating, by the processor, a design model by designing an integrated circuit using the signal simulation predicting information.

Abstract: Provided are a device and method for updating a register transfer level (RTL) power model for power consumption analysis of a semiconductor circuit by at least one processor. The method includes receiving a test scenario including a plurality of time slots, inputting the test scenario to an initial power model and identifying a first set of time slots related to a power state which is not defined by the initial power model among the plurality of time slots, determining a power value for a specific power state related to a second set of time slots which is a subset of the first set of time slots, and updating the initial power model on the basis of the specific power state and the determined power value. Each of the plurality of time slots is related to one power state.

Abstract: Provided is a bit-width optimization method for performing floating point to fixed point conversion (FFC) by at least one processor. The bit-width optimization method includes receiving a first floating-point value which represents a minimum value among floating-point values to be converted, receiving a second floating-point value which represents a maximum value among the floating-point values to be converted, receiving a maximum permissible error rate for performing FFC, calculating a minimum bit width of fixed-point notation which satisfies the maximum permissible error rate on the basis of the first floating-point value, the second floating-point value, and the maximum permissible error rate, and calculating a scale factor for FFC on the basis of the second floating-point value and the calculated minimum bit width.

Abstract: An apparatus and method for packet routing in a high-speed packet routing system. The apparatus includes an input unit and a control unit. The input unit temporarily stores an input packet and outputs the temporarily stored input packet to an output port determined by a previous router. The control unit determines an output port of a next router for the input packet.