Abstract: The disclosure provides, among other things, methods for producing and using 5′-chimeric RNAs and cDNAs. 5′-chimeric RNAs and cDNAs may be used, for example, for high-throughput analysis of the 5′-end sequences for RNA transcripts.

Abstract: The semiconductor memory device includes a plurality of first data sense amplifiers and a plurality of second data sense amplifiers. Each first data sense amplifier being a voltage sense amplifier, and each first data sense amplifier associated with data lines of a first type, which lead from bit line sense amplifiers. Each second data sense amplifier including a current sense amplifier and a voltage sense amplifier, and each second data sense amplifier associated with data lines of a second type, which lead from bit line sense amplifiers.

Abstract: A method for locking or prohibiting an access to at least one object in an electronic conferencing system, includes the steps of: a) initiating an electronic conference in the conference initiator system having an electronic whiteboard, the electronic whiteboard containing at least one object; b) participating conference participant systems in the electronic conference, thereby sharing the electronic whiteboard with the conference initiator system; c) sending a lock request corresponding to the object from a conference participant system to the conference initiator system in order to obtain the priority over the access to the object corresponding to the lock request from the conference initiator system or prohibit the access to the object performed by another conference participant system not having the priority; and d) giving a priority over an access to the object to the conference participant system according to a sequence of lock requests in response to the lock request.

Abstract: Disclosed is a method of manufacturing an image sensor having light sensitivity over a photodiode equal in area to that of a unit pixel. The image sensor includes an image sensor comprising: a first semiconductor substrate doped with a first conductive dopant; a first diffusion layer formed in the semiconductor substrate and doped with a second conductive dopant; a second diffusion layer formed in the semiconductor substrate adjacent the first diffusion layer and having a width wider than a width of the first diffusion layer; a third diffusion layer doped with the first conductive dopant and formed at an exposed surface of the semiconductor substrate in the first diffusion layer; a gate electrode formed on the exposed surface and having a first edge adjacent to the third diffusion layer; and a fourth diffusion layer doped with the second conductive dopant and formed at the exposed surface adjacent a second edge of the gate electrode, the fourth diffusion layer defining a gap with the second diffusion layer.

Abstract: Isolated nucleic acid molecules, designated MP nucleic acid molecules, which encode novel MP proteins from Corynebacterium glutamicum are described. The invention also provides antisense nucleic acid molecules, recombinant expression vectors containing MP nucleic acid molecules, and host cells into which the expression vectors have been introduced. The invention still further provides isolated MP proteins, mutated MP proteins, fusion proteins, antigenic peptides and methods for the improvement of production of a desired compound from C. glutamicurn based on genetic engineering of MP genes in this organism.

Abstract: A cleaning apparatus of a high-density plasma chemical vapor deposition chamber, and a cleaning method thereof, uniformly and sufficiently supplies a cleaning gas into a chamber to uniformly clean the chamber. The cleaning apparatus includes a chamber, an upper electrode provided in an upper portion of the chamber and applied with radio frequency energy, a lower electrode provided below the upper electrode and applied with radio frequency energy, a chuck provided below the upper electrode and formed thereon with the lower electrode to fix a wafer thereon, and three or more cleaning gas nozzles provided at regular intervals on the sidewall of the chamber around the chuck.

Abstract: A semiconductor memory device having reduced sensing noise and sensing current by reducing the number of cells activated by a word line is provided. The semiconductor memory device includes a memory cell array, which is segmented into a plurality of memory cell groups in a column direction, and a plurality of sub-word line drivers for selectively activating the sub-word line of a corresponding memory cell group in response to a group selection signal. The semiconductor memory device prevents sensing operation from occurring in a memory cell group which is not selected, while sensing operation is performed in a memory cell group which is selected by the group selection signal.

Abstract: Disclosed is an overlay accuracy measurement mark used in measuring an overlay accuracy between any two selected device patterns in a semiconductor device having two or more multi-patterns. The mark is applied to a semiconductor device comprising a first pattern which is first formed, and second patterns consisting of at least one or more target patterns for alignment with the first pattern, which are formed after the formation of the first pattern.

Abstract: An input buffer that can operate with Low Voltage Transistor-Transistor Logic (LVTTL) and with Stub Series Terminated transceiver Logic (SSTL) includes a differential amplifier that differentially amplifies a reference voltage and an external input signal. A switching system is coupled to the differential amplifier, to supply an external power supply voltage to the differential amplifier under SSTL operating conditions and to supply an internal power supply voltage to the differential amplifier under LVTTL operating conditions. An internal power supply voltage generator is responsive to the external power supply voltage, to generate the internal power supply voltage therefrom. The internal power supply voltage generator supplies the internal power supply voltage to the switching system. The switching system preferably includes a first switch that supplies the external power supply voltage to the differential amplifier in response to an SSTL control signal.

Abstract: Disclosed is an overlay accuracy measurement mark used in measuring an overlay accuracy between any two selected device patterns in a semiconductor device having two or more multi-patterns. The mark is applied to a semiconductor device comprising a first pattern which is first formed, and second patterns consisting of at least one or more target patterns for alignment with the first pattern, which are formed after the formation of the first pattern.

Abstract: The present invention provides a photomask for removing the notching phenomenon, which occurs when a photoresist pattern is formed on a highly reflective under layer.In accordance with the present invention, there is disclosed a photomask used in forming photoresist patterns in a semiconductor device, wherein said semiconductor device includes a inclined metal layer by a topology of underlayers, said photomask comprising: a transparent substrate; main patterns formed on said transparent substrate; and dummy patterns formed on said transparent substrate, wherein said dummy patterns positioned between main patterns and positioned in an area corresponding to said inclined metal layer, and wherein said dummy patterns have a predetermined width and interval so that said dummy patterns leave no corresponding photoresist pattern, whereby said dummy patterns remove a notching phenomenon by attenuating the light intensity from a light source.

Abstract: The present invention can improve the limits of the resolution in a stepper by forming some portions or whole portions of the edges of the photomask pattern into a constant saw toothed structure so that the interference phenomenon of the wavelength at its maximum is offsetted.

Abstract: The present invention relates to a transistor in a semiconductor device and method of making thereof which can improve the driving speed, by forming the junction region thicker than the channel and LDD regions so as to reduce the resistance itself of the junction region.

Abstract: This invention relates to a method of manufacturing a transistor which can form a junction having shallow junction depth and accomplish high trans conductance by forming a N.sup.+ region on a silicon substrate to suppress short channel effect and forming a P.sup.-- layer on the N.sup.+ region using a boron silicate glass layer(BSG) in manufacturing a p-type transistor.

Abstract: A photomask is fabricated by forming a scribe line at the four sides of a product die pattern and forming vernier patterns at four corners. The vernier pattern is formed of a regular square area and a regular square band-shaped area. A reticle rotation error of an exposer, X and Y-axis stepping error, a bending error of the lens and a pattern error formed on the wafer due to the fabricating error of the photomask can be found by developing the overlapped vernier patterns which are exposed several times using the photomask.

Abstract: A method for setting the blind of a stepper comprising the steps of: forming a first pattern which is made on a wafer by said blind, and a second pattern which is made on the wafer by chrome patterns of a reticle; comparing said first pattern with said second pattern; and measuring a setting error of said blind from the difference between said first pattern and second pattern.

Abstract: There are disclosed photomasks for the measurement of resolution of exposure equipment, comprising two superimposed patterns, each of which has a plurality of identical sub-patterns and is symmetric on its central axis, the two being aligned in such a way that the spaces between their opposite, corresponding sub-patterns become wider or narrower, in sequence, or comprising a plurality of concentric patterns which are interconnected by connecting films, the connecting films being formed in the space between the concentric patterns.

Abstract: There is disclosed an exposure mask useful for a lithography process for semiconductor device. The exposure mask consists of a plurality of spaced apart light screen patterns and a plurality of spaced apart subsidiary patterns on a transparent substrate, each of the subsidiary patterns being positioned between the light screen patterns and at an area where a necking effect is expected upon a forming photosensitive film pattern over a deteriorated topology using a light exposure mask.

Abstract: A reticle which can detect precisely an error in reticle rotation. A first main vernier is formed at an outer side of the right end of the unit field and a sub vernier is formed at the left end. A second main vernier is formed at the outer side of the upper end of the unit field, and a sub vernier is formed at the lower end. Another reticle uses a first main vernier on the right scribe lane zone, and a sub vernier on the left. A second vernier is formed on the upper side, with its sub on the lower side. These verniers are used together to determine an error.

Abstract: A reticle provided with mother and son verniers for measuring a rotation of the reticle, the mother vernier being disposed at a portion of the reticle, which portion corresponds to a center of a lens equipped in the exposure equipment using the reticle. At least one pair of son verniers are disposed at areas of the reticle uniformly spaced apart from the mother vernier along a horizontal line passing through the mother vernier, respectively. The reticle provides a means and method of minimizing an error caused by a distortion of a lens and precisely measuring a rotation error.