Patents by Inventor Joon Hyeok Byeon

Joon Hyeok Byeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ESD protection silicon controlled rectifier device
    Patent number: 10879231
    Abstract: An ESD protection SCR device includes an epitaxial layer provided on a P-type semiconductor substrate, the epitaxial layer having the P-type conductivity, element isolation layers provided on the epitaxial layer, the element isolation layers dividing the epitaxial layer into an anode region and a cathode region, a first well of an N-type conductivity, provided in a portion of the epitaxial layer corresponding to the anode region, a first impurity region provided on a surface of the first well, the first impurity region being connected to an anode terminal and having a high concentration P-type conductivity, a second well of the P-type conductivity, provided in a portion of the epitaxial layer corresponding to the cathode region, a second impurity region provided on a surface of the second well, the second impurity region being connected to a cathode terminal and having a high concentration N-type conductivity, and a floating well of the N-type conductivity, buried in the epitaxial layer.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: December 29, 2020
    Assignee: DB HITEK CO., LTD.
    Inventors: Seok Soon Noh, Joon Tae Jang, Joon Hyeok Byeon, Young Chul Kim
  • ESD PROTECTION SILICON CONTROLLED RECTIFIER DEVICE
    Publication number: 20190319024
    Abstract: An ESD protection SCR device includes an epitaxial layer provided on a P-type semiconductor substrate, the epitaxial layer having the P-type conductivity, element isolation layers provided on the epitaxial layer, the element isolation layers dividing the epitaxial layer into an anode region and a cathode region, a first well of an N-type conductivity, provided in a portion of the epitaxial layer corresponding to the anode region, a first impurity region provided on a surface of the first well, the first impurity region being connected to an anode terminal and having a high concentration P-type conductivity, a second well of the P-type conductivity, provided in a portion of the epitaxial layer corresponding to the cathode region, a second impurity region provided on a surface of the second well, the second impurity region being connected to a cathode terminal and having a high concentration N-type conductivity, and a floating well of the N-type conductivity, buried in the epitaxial layer.
    Type: Application
    Filed: April 16, 2019
    Publication date: October 17, 2019
    Inventors: Seok Soon Noh, Joon Tae Jang, Joon Hyeok Byeon, Young Chul Kim