Patents by Inventor Joon Hyeon Lee

Joon Hyeon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240155938
    Abstract: An organic light-emitting device according to the present invention uses a pyrene derivative compound having a characteristic structure as a host in a light-emitting layer to realize a long-lifespan and high-efficiency organic light-emitting device having excellent light-emitting characteristics in terms of lifespan and luminescence efficiency. Accordingly, the organic light-emitting device can be usefully applied, in the industrial aspect, for various display devices such as flat panel, flexible, and wearable displays, as well as lighting devices.
    Type: Application
    Filed: February 15, 2022
    Publication date: May 9, 2024
    Inventors: Se-jin LEE, Si-in KIM, Seok-bae PARK, Hee-dae KIM, Yeong-tae CHOI, Seung-soo LEE, Ji-yung KIM, Kyeong-hyeon KIM, Kyung-tae KIM, Myeong-jun KIM, Tae-gyun LEE, Joon-ho KIM
  • Patent number: 11951207
    Abstract: The present invention provides a stable liquid pharmaceutical formulation containing: an antibody or its antigen-binding fragment; a surfactant; a sugar or its derivative; and a buffer. The stable liquid pharmaceutical formulation according to the present invention has low viscosity while containing a high content of the antibody, has excellent long-term storage stability based on excellent stability under accelerated conditions and severe conditions, and may be administered subcutaneously.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: April 9, 2024
    Assignee: Celltrion Inc.
    Inventors: Joon Won Lee, Won Yong Han, Su Jung Kim, Jun Seok Oh, So Young Kim, Su Hyeon Hong, Yeon Kyeong Shin
  • Publication number: 20240090318
    Abstract: The present invention relates to a novel heterocyclic compound usable in an organic light-emitting device and to an organic light-emitting device comprising same, wherein [chemical formula A] is as described in the detailed description of the invention.
    Type: Application
    Filed: December 28, 2021
    Publication date: March 14, 2024
    Inventors: Se-Jin LEE, Seok-Bae PARK, Si-In KIM, Hee-Dae KIM, Yeong-Tae CHOI, Ji-Yung KIM, Kyung-Tae KIM, Myeong-Jun KIM, Kyeong-hyeon KIM, Seung-soo LEE, Tae Gyun LEE, Joon-Ho KIM
  • Patent number: 11919122
    Abstract: A substrate processing apparatus includes: a conveyor belt configured to have an outer surface on which a bottom surface of a substrate is seated; and a polishing head unit configured to face an upper surface of the substrate, wherein the polishing head unit includes: a polishing head connected to a driver; a polishing pad configured to face the polishing head; a polishing pad fixing ring disposed between the polishing head and the polishing pad; and a temperature sensor configured to overlap the polishing pad fixing ring and to be spaced apart from the polishing pad fixing ring.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: March 5, 2024
    Assignees: SAMSUNG DISPLAY CO., LTD., KCTECH CO., LTD.
    Inventors: Seung Bae Kang, Sung Hyeon Park, Jung Gun Nam, Joon-Hwa Bae, Kyung Bo Lee, Keun Woo Lee, Woo Jin Cho, Byoung Kwon Choo
  • Patent number: 7537998
    Abstract: Forming salicide in a semiconductor device includes the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxide film; forming a conductive layer and a nitride based hard mask layer, and then selectively removing the conductive layer, the hard mask layer, the first gate oxide film, and the second gate oxide film, thereby forming gate electrodes and simultaneously exposing an active region of the salicide region; forming a spacer oxide film on an upper surface, except for the hard mask layer, of a second resultant structure; selectively removing the spacer oxide film, thereby forming a spacer and simultaneously exposing the active region of the salicide region; removing the hard mask layer; and forming a salicide film on the upper surfaces of the gate electrodes and on the surface of the active region in the salicide region.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: May 26, 2009
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Joon Hyeon Lee, Woon Yong Kim
  • Publication number: 20070264811
    Abstract: Forming salicide in a semiconductor device includes the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxide film; forming a conductive layer and a nitride based hard mask layer, and then selectively removing the conductive layer, the hard mask layer, the first gate oxide film, and the second gate oxide film, thereby forming gate electrodes and simultaneously exposing an active region of the salicide region; forming a spacer oxide film on an upper surface, except for the hard mask layer, of a second resultant structure; selectively removing the spacer oxide film, thereby forming a spacer and simultaneously exposing the active region of the salicide region; removing the hard mask layer; and forming a salicide film on the upper surfaces of the gate electrodes and on the surface of the active region in the salicide region.
    Type: Application
    Filed: July 24, 2007
    Publication date: November 15, 2007
    Inventors: Joon Hyeon LEE, Woon Yong KIM
  • Patent number: 7262103
    Abstract: Disclosed is a method for forming salicide in a semiconductor device. The method comprises the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxide film; forming a conductive layer and a nitride based hard mask layer, and then selectively removing the conductive layer, the hard mask layer, the first gate oxide film, and the second gate oxide film, thereby forming gate electrodes and simultaneously exposing an active region of the salicide region; forming a spacer oxide film on an upper surface, except for the hard mask layer, of a second resultant structure; selectively removing the spacer oxide film, thereby forming a spacer and simultaneously exposing the active region of the salicide region; removing the hard mask layer; and forming a salicide film on the upper surfaces of the gate electrodes and on the surface of the active region in the salicide region.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: August 28, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Joon Hyeon Lee, Woon Yong Kim
  • Patent number: 7148150
    Abstract: The present invention relates to a method of forming a metal line layer in a semiconductor device comprising step of depositing a metal line layer on a semiconductor structure; forming an insulating film and a photoresist material on the metal line layer in a sequential manner, patterning the metal line layer by using the photoresist material and the insulating film as a mask; removing the photoresist material; and etching the insulating film in an isotropic manner. According to the present invention, since metal polymers and metal residues are perfectly removed during the process of forming the metal line layer, it is possible to remove sources, which induce the bridge phenomena. Therefore, it is possible to remarkably improve reliability of a semiconductor device.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: December 12, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Joon Hyeon Lee
  • Patent number: 7078339
    Abstract: The present invention is provided to form a metal line layer in a semiconductor device, wherein at least one conductive layer of a plurality of conductive layers is etched, a side wall oxide film is formed on side walls of some conductive layers of the etched conductive layers, and then the other conductive layers are etched. According to the present invention, since it is possible to prevent attacks against the side walls, which may occur due to sputtering and bending of plasma ions, it is possible to enhance yield and reliability of a semiconductor device.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: July 18, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Joon Hyeon Lee
  • Patent number: 7030507
    Abstract: Disclosed is a test pattern comprising: lower metal patterns for test formed in such a manner that crank-type patterns are arranged in sequence overlapping on each other in a view along a vertical line; hole patterns formed in such a manner that each of the hole patterns exposes either a front end and a rear end of each crank-type lower metal pattern; and upper metal patterns formed in such a manner that each upper metal pattern interconnects a front end of each lower metal pattern and a rear end of an adjacent lower metal pattern overlapping on each other in a view along a vertical line.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: April 18, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Joon Hyeon Lee
  • Patent number: 7018927
    Abstract: An isolation film for semiconductor devices is formed from a pad oxide film and a pad nitride film on a substrate, etching the pad nitride film, the pad oxide film and the substrate to form a trench in an active region of the substrate; forming a sidewall oxide film on the surface of the trench; removing the pad nitride film; forming a linear nitride film on the sidewall oxide film and the pad oxide film; removing a portion of the pad oxide film on the substrate; removing the exposed pad oxide film to expose the field region of the substrate; oxidizing the exposed field region to form an oxide film; removing the sidewall oxide film to expose the active region of the substrate; and forming a silicon epitaxial layer serving as an active layer on the exposed active region of the substrate to the same height as the oxide film.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: March 28, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Joon Hyeon Lee
  • Patent number: 6927142
    Abstract: Disclosed is a method of fabricating a capacitor of a semiconductor device, which can produce an MIM capacitor in which an insulator film is formed to have a positive slope by means of a polymer, thereby preventing leakage of current in the capacitor. The method comprises the steps of: sequentially forming a first metal film, an insulator film, and a second metal film on a semiconductor substrate; patterning a second metal film to form an upper electrode; etching the insulator film using the upper electrode as a mask, and simultaneously forming a polymer at one side of the upper electrode; etching the insulator film which is not protected by the polymer, thereby removing the insulator film; and removing the polymer formed at said one side of the upper electrode.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: August 9, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Joon Hyeon Lee, Seung Hee Han
  • Publication number: 20040142532
    Abstract: Disclosed is a method for forming salicide in a semiconductor device. The method comprises the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxide film; forming a conductive layer and a nitride based hard mask layer, and then selectively removing the conductive layer, the hard mask layer, the first gate oxide film, and the second gate oxide film, thereby forming gate electrodes and simultaneously exposing an active region of the salicide region; forming a spacer oxide film on an upper surface, except for the hard mask layer, of a second resultant structure; selectively removing the spacer oxide film, thereby forming a spacer and simultaneously exposing the active region of the salicide region; removing the hard mask layer; and forming a salicide film on the upper surfaces of the gate electrodes and on the surface of the active region in the salicide region.
    Type: Application
    Filed: December 18, 2003
    Publication date: July 22, 2004
    Inventors: Joon Hyeon Lee, Woo Yong Kim
  • Publication number: 20040110358
    Abstract: The present invention relates to a method for forming an isolation film for semiconductor devices.
    Type: Application
    Filed: July 18, 2003
    Publication date: June 10, 2004
    Inventor: Joon Hyeon Lee
  • Patent number: 6746936
    Abstract: The present invention relates to a method for forming an isolation film for semiconductor devices.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: June 8, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventor: Joon Hyeon Lee