Patents by Inventor Joon-hyock Choi

Joon-hyock Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7714421
    Abstract: A small structure which uses bonding wires to prevent disturbance and provide support and a method of fabricating the same are provided. The small structure includes a floating body having a plurality of first contact pads, a base having a plurality of second contact pads, and a plurality of bonding wires electrically connecting the first and second contact pads and elastically supporting the floating body. The method of fabricating the small structure includes preparing a base, forming a sacrificial layer on the base, disposing a floating body on the sacrificial layer, connecting the base and the floating body with bonding wires, and removing the sacrificial layer. Thereby, fabrication costs of the small structure are reduced.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: May 11, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-pal Kim, Yong-chul Cho, Byeung-leul Lee, Sang-woo Lee, Joon-hyock Choi
  • Patent number: 7230307
    Abstract: A vertical offset structure and a method for fabricating the same. The vertical offset structure includes a substrate; a fixed electrode fixing portion formed on the substrate; a fixed electrode moving portion formed at a position away from an upper portion of the substrate by a predetermined distance; a spring portion for connecting the fixed electrode fixing portion and the fixed electrode moving portion to each other so that the fixed electrode moving portion moves into a direction substantially perpendicular to a plate surface of the substrate; a movable electrode located away from the upper portion of the substrate by a predetermined distance to have a predetermined interval horizontal to the fixed electrode moving portion; and a cap wafer bonded to a predetermined area of one of the fixed electrode moving portion and the movable electrode.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: June 12, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-woo Lee, Byeung-leul Lee, Jong-pal Kim, Joon-hyock Choi
  • Publication number: 20060023995
    Abstract: A vertical offset structure and a method for fabricating the same. The vertical offset structure includes a substrate; a fixed electrode fixing portion formed on the substrate; a fixed electrode moving portion formed at a position away from an upper portion of the substrate by a predetermined distance; a spring portion for connecting the fixed electrode fixing portion and the fixed electrode moving portion to each other so that the fixed electrode moving portion moves into a direction substantially perpendicular to a plate surface of the substrate; a movable electrode located away from the upper portion of the substrate by a predetermined distance to have a predetermined interval horizontal to the fixed electrode moving portion; and a cap wafer bonded to a predetermined area of one of the fixed electrode moving portion and the movable electrode.
    Type: Application
    Filed: July 19, 2005
    Publication date: February 2, 2006
    Inventors: Sang-woo Lee, Byeung-leul Lee, Jong-pal Kim, Joon-hyock Choi
  • Publication number: 20060022322
    Abstract: A small structure which uses bonding wires to prevent disturbance and provide support and a method of fabricating the same are provided. The small structure includes a floating body having a plurality of first contact pads, a base having a plurality of second contact pads, and a plurality of bonding wires electrically connecting the first and second contact pads and elastically supporting the floating body. The method of fabricating the small structure includes preparing a base, forming a sacrificial layer on the base, disposing a floating body on the sacrificial layer, connecting the base and the floating body with bonding wires, and removing the sacrificial layer. Thereby, fabrication costs of the small structure are reduced.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 2, 2006
    Inventors: Jong-pal Kim, Yong-chul Cho, Byeung-leul Lee, Sang-woo Lee, Joon-hyock Choi
  • Publication number: 20060010978
    Abstract: A MEMS gyroscope with coupling springs and mass bodies symmetrical to one another and relatively movable in a vertical direction with respect to a substrate, where a coupling spring connects the mass bodies and moves the mass bodies in a vertical direction as another one of the mass bodies moves in the opposite vertical direction.
    Type: Application
    Filed: July 18, 2005
    Publication date: January 19, 2006
    Inventors: Sang-woo Lee, Byeung-leul Lee, Jong-pal Kim, Joon-hyock Choi
  • Patent number: 6719918
    Abstract: A method of reducing notching during reactive ion etching (RIE) is provided. The method is useful when RIE is performed to pass through a silicon layer on a multi-layered structure on which the silicon layer, an insulating layer and a silicon substrate are sequentially deposited. The method includes the steps of: forming an insulating layer on a silicon substrate; forming trenches on the insulating layer to expose the silicon substrate; forming a silicon layer on the insulating layer to fill the trenches; and patterning the silicon layer to form first etch regions, which pass through the silicon layer, to include the trenches. According to the method, it is possible to remarkably reduce notching without depositing a metal layer, when a multi-layered structure including a silicon layer which is etched to be passed through during RIE is fabricated.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: April 13, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byeung-leul Lee, Taek-ryong Chung, Joon-hyock Choi, Won-youl Choi, Kyu-dong Jung, Sang-woo Lee
  • Publication number: 20020125211
    Abstract: A method of reducing notching during reactive ion etching (RIE) is provided. The method is useful when RIE is performed to pass through a silicon layer on a multi-layered structure on which the silicon layer, an insulating layer and a silicon substrate are sequentially deposited. The method includes the steps of: forming an insulating layer on a silicon substrate; forming trenches on the insulating layer to expose the silicon substrate; forming a silicon layer on the insulating layer to fill the trenches; and patterning the silicon layer to form first etch regions, which pass through the silicon layer, to include the trenches. According to the method, it is possible to remarkably reduce notching without depositing a metal layer, when a multi-layered structure including a silicon layer which is etched to be passed through during RIE is fabricated.
    Type: Application
    Filed: December 26, 2001
    Publication date: September 12, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byeung-Leul Lee, Taek-Ryong Chung, Joon-Hyock Choi, Won-Youl Chol, Kyu-Dong Jung, Sang-Woo Lee