Abstract: A display device includes a base substrate including a first sub-pixel area, a second sub-pixel area, and a third sub-pixel area, first to third thin film transistors on the base substrate and including first to third active patterns, respectively, first to third pixel electrodes electrically connected to the first to third thin film transistors, respectively and in the first to third sub-pixel areas, respectively, a blue light emitting layer on the first to third pixel electrodes and configured to emit a blue light, a first color conversion pattern in the first sub-pixel area on the blue light emitting layer, a second color conversion pattern in the second sub-pixel area on the blue light emitting layer, and a red color filter layer between the blue light emitting layer and the first to third active patterns.

Abstract: A display apparatus including a base substrate, a first thin film transistor disposed on the base substrate, a via insulation layer disposed on the first thin film transistor, and a light emitting structure disposed on the via insulation layer. The first thin film transistor includes a first gate electrode, an oxide semiconductor overlapped with the first gate electrode, and including tin (Sn), an etch stopper disposed on the oxide semiconductor and including an oxide semiconductor material which does not include tin (Sn), a first source electrode making contact with the oxide semiconductor, and a first drain electrode making contact with the oxide semiconductor, and spaced apart from the first source electrode.

Abstract: A display device comprises a substrate; a driving transistor including a first active layer and a switching transistor including a second active layer, the first active layer and the second active layer being disposed on the substrate; a first gate insulating layer disposed on the first active layer of the driving transistor and the second active layer of the switching transistor; first and second gate electrodes disposed on the first gate insulating layer to overlap the first active layer of the driving transistor and the second active layer of the switching transistor, respectively; a first interlayer insulating layer disposed on the first gate electrode and the second gate electrode; and a second interlayer insulating layer disposed on the first interlayer insulating layer to overlap the first active layer without overlapping the second active layer in a plan view.

Abstract: A position sensing circuit that can be used with a position control device including a differential sensing coil unit having a first sensing coil and a second sensing coil disposed to face a conductor disposed on one side of a lens barrel. The position sensing circuit includes: a differential oscillation circuit generating a first oscillation signal having a first amplitude based on a first inductance of the first sensing coil, variable according to positional movement of the conductor, and a second oscillation signal having a second amplitude based on a second inductance of the second sensing coil, variable according to positional movement of the conductor; an amplitude detection circuit detecting the first amplitude of the first oscillation signal and the second amplitude of the second oscillation signal; and a signal processing circuit calculating the first amplitude and the second amplitude to calculate a position value.

Abstract: An infrared image sensor includes: a plurality of reference circuits configured to provide a plurality of reference analog values to a plurality of bolometer cells, respectively; a front-end analog circuit configured to collect a plurality of output analog values according to the plurality of reference analog values; and a noise suppression circuit configured to switch a correspondence between the plurality of bolometer cells and the plurality of reference analog values at unit time intervals.

Abstract: An infrared image sensor includes: a plurality of reference circuits configured to provide a plurality of reference analog values to a plurality of bolometer cells, respectively; a front-end analog circuit configured to collect a plurality of output analog values according to the plurality of reference analog values; and a noise suppression circuit configured to switch a correspondence between the plurality of bolometer cells and the plurality of reference analog values at unit time intervals.

Abstract: A position sensing circuit that can be used with a position control device including a differential sensing coil unit having a first sensing coil and a second sensing coil disposed to face a conductor disposed on one side of a lens barrel. The position sensing circuit includes: a differential oscillation circuit generating a first oscillation signal having a first amplitude based on a first inductance of the first sensing coil, variable according to positional movement of the conductor, and a second oscillation signal having a second amplitude based on a second inductance of the second sensing coil, variable according to positional movement of the conductor; an amplitude detection circuit detecting the first amplitude of the first oscillation signal and the second amplitude of the second oscillation signal; and a signal processing circuit calculating the first amplitude and the second amplitude to calculate a position value.

Abstract: A position detecting device includes a first hall device and a second hall device; a subtractor to subtract a second hall voltage generated by the second hall device from a first hall voltage generated by the first hall device to generate a subtraction voltage; an adder to add the first hall voltage to the second hall voltage to generate an addition voltage; and a divider to calculate a ratio of the addition voltage to the subtraction voltage in accordance with a charging time of a capacitor using the addition voltage and a discharging time of the capacitor using the subtraction voltage.

Abstract: A dual-slope analog-to-digital converter includes a switching circuit, an integrating circuit, a dual comparison circuit, and a control circuit. The integrating circuit is configured to perform a charging operation having a first slope, based on a magnitude of an input voltage selected by the switching circuit, and a discharging operation having a second slope, based on a magnitude of the reference voltage selected by the switching circuit, and output a first voltage. The dual comparison circuit is configured to output a first comparison signal by comparing the first voltage with a first reference voltage and output a second comparison signal by comparing a second reference voltage, higher than the first reference voltage, with the first voltage. The control circuit is configured to output a digital value corresponding to the magnitude of the input voltage, based on a first count value and a second count value.

Abstract: An apparatus and method thereof are described to measure alternating current (AC) power, including: an AC voltage measurement circuit, an in-phase/quadrature (I/Q) direct down converter, an analog/digital converter, and an AC power calculator. The AC voltage measurement circuit is configured to measure first and second AC positive voltages and first and second AC negative voltages from an AC voltage source. The I/Q direct down converter is configured to directly convert each of the first and second AC positive voltages and the first and second AC negative voltages into an I-signal and a Q-signal orthogonal to each other using down conversion. The analog/digital converter is configured to convert the I-signal and the Q-signal into I-data and Q-data, respectively. The AC power calculator is configured to calculate the AC power using the I-data and the Q-data.

Abstract: An apparatus and method thereof are described to measure alternating current (AC) power, including: an AC voltage measurement circuit, an in-phase/quadrature (I/Q) direct down converter, an analog/digital converter, and an AC power calculator. The AC voltage measurement circuit is configured to measure first and second AC positive voltages and first and second AC negative voltages from an AC voltage source. The I/Q direct down converter is configured to directly convert each of the first and second AC positive voltages and the first and second AC negative voltages into an I-signal and a Q-signal orthogonal to each other using down conversion. The analog/digital converter is configured to convert the I-signal and the Q-signal into I-data and Q-data, respectively. The AC power calculator is configured to calculate the AC power using the I-data and the Q-data.

Abstract: A reset signal generator may include a voltage divider dividing a voltage level of a driving voltage, a reference voltage generator generating a reference voltage by performing a switching operation on the driving voltage depending on a voltage level of the divided driving voltage from the voltage divider, and a comparator comparing the voltage level of the divided driving voltage and the reference voltage to output a reset signal depending on the comparison result. The integrated circuit includes the reset signal generator and a controller resetting a control operation depending on the reset signal.

Abstract: There are provided a frequency generation apparatus and a frequency generation method. The frequency generation apparatus includes a current generation unit varying an amount of current with respect to a temperature change; a capacitor in which charges are charged by the current generation unit; a discharge circuit unit comparing a charging voltage of the capacitor with a previously set first reference voltage and discharging the capacitor; and an output signal generation unit comparing the charging voltage of the capacitor with a previously set second reference voltage and generating an output signal, wherein the current generation unit varies the amount of current so as to maintain a constant frequency.

Abstract: A wireless communications terminal includes: an RF wake-up detection unit detecting a first RF signal including an RF ID for waking up; and a wireless communications unit waking up when the RF ID included in the first RF signal detected by the RF wake-up detection unit matches a pre-set reference ID in a sleep mode.

Abstract: An ozone generating device includes three or more cooling channels each having a through-hole formed in a central region thereof and a coolant flow path formed therein. The cooling channels are arranged side by side such that the through-holes thereof overlap with one another. The ozone generating device further includes electric discharge units interposed between the cooling channels adjoining each other and configured to generate electric discharge when applied with a high voltage. Each of the electric discharge units has a central hole formed in alignment with the through-hole. The ozone generating device is configured such that, when the electric discharge units are applied with a high voltage with the cooling channels kept grounded, oxygen supplied to the electric discharge units is decomposed into ozone which in turn is discharged through an internal space defined by the through-hole and the central hole.

Abstract: A wireless communications terminal includes: an RF wake-up detection unit detecting a first RF signal including an RF ID for waking up; and a wireless communications unit waking up when the RF ID included in the first RF signal detected by the RF wake-up detection unit matches a pre-set reference ID in a sleep mode.

Abstract: There is provided a low drop-out regulator. The low drop-out regulator includes an amplifier including an odd number of operational amplifiers connected to one another in series, and an output unit including a pass transistor operated by an output from the amplifier and generating an output voltage to be applied to a load, wherein the pass transistor is an N-channel transistor, and the amplifier controls a feedback loop gain between an output terminal of one of the odd number of operational amplifiers and the output unit. The feedback loop gain may be controlled independently from the trans-conductance of the pass transistor, whereby the stable output voltage may be generated, even in the case that the load and the input voltage are changed, and the design parameter may be simplified.

Abstract: The present invention discloses an impedance matching apparatus. The impedance matching apparatus includes: a multilayer printed circuit board; a signal line including a plurality of signal layers with the same pitch and formed by sequentially arranging the plurality of signal layers on the multilayer printed circuit board; and a ground plane including a plurality of ground layers, wherein the plurality of ground layers are arranged to get closer to a bottom surface of the multilayer printed circuit board from a region corresponding to one side of the signal line to a region corresponding to the other side of the signal line. The impedance matching apparatus can implement a line width without any problem of a process yield by determining specific impedance by a distance between the signal layer and the ground layer formed in corresponding positions, thereby improving the process yield.

Abstract: A wireless apparatus having a non-electric power-type wake-up function that operates a wake-up circuit waking-up a microprocessor for communications without power. There is provided a wireless apparatus having a wake-up function, including: a wake-up unit that has a rectifying circuit having elements configured as passive elements and rectifies preset first wireless signals to transmit wake-up signals; and a wireless communications unit that is woken-up by the wake-up signals from the wake-up unit to perform communications using preset second wireless signals, in a sleep mode.

Abstract: Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1?; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2?; a differential output terminal that outputs differential output signals Vout+ and Vout? generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.