Abstract: A method and apparatus for controlling power in a low-power multi-core system, including receiving task information from an Operation System (OS) kernel upon start and end of a task, estimating a future CPU usage using a current CPU usage in the task information, monitoring memory-related information in the task information, comparing a change in the current CPU usage with the monitored memory-related information, establishing a policy for power control based on the estimated CPU usage and the monitored memory-related information, and controlling on/off of multiple cores according to the established policy. By doing so, it is possible to solve the problems caused by performing DPM using only the CPU usage.

Abstract: A touch panel includes a dummy electrode capable of protecting a circuit included in the touch panel for shielding against static electricity.

Abstract: A power supply has a primary side and a secondary side electrically insulated from each other. A switching operation based on a switching of the primary side is controlled according to the power transmitted to the secondary side, and the switching operation is converted at a time earlier than a switching conversion time of the primary side by a predetermined time.

Abstract: A power supplying apparatus may be capable of switching off a synchronous rectifier on a secondary side in advance by predicting a switching-on time on a primary side. The power supplying apparatus may include: a power converting unit switching power input to the primary side and transferring the power to the secondary side; and a synchronous rectifying unit formed on the secondary side, synchronized with the switching of the power converting unit to perform a rectification switching operation, thereby rectifying the power transferred from the power converting unit, and changing the rectification switching operation before a switching change point of the power converting unit depending on a preset timing.

Abstract: A circuit for driving a synchronous rectifier may include a voltage level detecting unit detecting a voltage level of the synchronous rectifier; an on/off signal generating unit generating an on signal controlling the synchronous rectifier to be turned on when the voltage level detected by the voltage level detecting unit is decreased to a voltage level equal to or less than a preset reference voltage level, and generating an off signal controlling the synchronous rectifier to be turned off when the voltage level detected by the voltage level detecting unit is increased to a voltage level exceeding the reference voltage level; a minimum time determining unit controlling the synchronous rectifier to be turned on during a preset first period; and a blanking time determining unit controlling the synchronous rectifier so as not to be turned on during a preset second period after the synchronous rectifier has been turned off.

Abstract: The present invention relates to a silicon DBR structure-integrated light device, and a preparation method thereof, and more specifically, to a silicon DBR structure-integrated light device or vertical cavity light emitting diode, and a preparation method thereof, enabling preparation by a small number of layers and capable of reducing process time and costs due to a large contrast in refractive index of a silicon DBR structure formed by depositing silicon in a slanted or vertical manner.

Abstract: The present invention relates to an IC circuit. In an embodiment, an IC circuit includes: an RT terminal connected to an external; a current mirroring unit conducting a channel current between internal voltage power and the RT terminal and generating an internal reference current mirrored with the channel current; a negative feedback unit receiving the internal reference current, equalizing voltages of an RT terminal connection terminal and an internal reference current output terminal of the current mirroring unit to make the internal reference current constant, and providing the internal reference current inside the IC circuit; and an IC state indicating unit having a transistor, which operates complementarily with the current mirroring unit, connected between the RT terminal and a ground and providing the state of an IC or a system to the RT terminal by being linked with the complementary operation of the current mirroring unit.

Abstract: Provided is an electrode panel of a touch panel and a method of manufacturing the same, the method, including: forming a plurality of electrode pattern cells on a substrate to be space apart from each other; forming an insulating layer on the electrode pattern cells; forming a hole on the insulating layer; and forming a bridge electrode and fills the hole with a conductive material.

Abstract: A clothing dryer having an improved structure of a drainage unit thereof, including: a body; a drum; a base that is disposed at a lower portion of the drum; a first water tub that is mounted on the base to collect condensate water generated when a drying operation is performed; and a plurality of drainage pipes that are combined with one side of the first water tub and cause the condensate water to move, wherein, in order to change a position at which the plurality of drainage pipes and the first water tub are combined with each other, the first water tub is combined with edges of the base so that at least a part of the first water tub is able to be exposed to an outside.

Abstract: A log-periodic dipole array antenna according to one exemplary embodiment of the present disclosure includes a dielectric substrate, a radiating element having a plurality of lines extending from a center to an outer side and symmetrically arranged on the dielectric substrate based on the center, so as to resonate in a first frequency band and a second frequency band, the plurality of lines being connected at the center or the outer side of the radiating element in an alternating manner, the lines becoming longer going from up to down of the radiating element fed according to a predetermined long-periodic ratio, and a band stopper formed on one point for connecting the lines to each other

Abstract: A power control method of a Central Processing Unit (CPU) in a multi-core system. The power control method includes acquiring current usage information of the CPU and system information, estimating a CPU usage of a next time interval based on the acquired current usage information, calibrating the estimated CPU usage of the next time interval based on the acquired system information, and determining a power control mode based on at least one of the acquired system information and the calibrated CPU usage of the next time interval.

Abstract: A method of operating an Internet protocol (IP) address allocates, creates, and processes an interface identifier (ID) of an IP address area. In the allocation, the IP address area includes a subnet prefix area and an Interface ID area, and certain bits of the Interface ID area are used as an index area of a subnet gateway. The allocation is implemented in order from the higher layer to the lower layer so that the Interface ID area is sequentially allocated from the higher bits for the index areas of the respective layers. The combination of the certain bits of the allocated Interface ID and the subnet prefix area of the IP address area is used as the subnet ID of the subnet layers. The lowest subnet gateway allocates the Interface ID to terminating equipment to access the IP network based on a format of the IP address.

Abstract: A method of operating an Internet protocol (IP) address allocates, creates, and processes an interface identifier (ID) of an IP address area. In the allocation, the IP address area includes a subnet prefix area and an Interface ID area, and certain bits of the Interface ID area are used as an index area of a subnet gateway. The allocation is implemented in order from the higher layer to the lower layer so that the Interface ID area is sequentially allocated from the higher bits for the index areas of the respective layers. The combination of the certain bits of the allocated Interface ID and the subnet prefix area of the IP address area is used as the subnet ID of the subnet layers. The lowest subnet gateway allocates the Interface ID to terminating equipment to access the IP network based on a format of the IP address.

Abstract: A control panel assembly and a laundry treating apparatus having the same, the control panel assembly including a control panel, a Printed Circuit Board (PCB) provided at a rear side of the control panel, and a PCB housing configured to fix the PCB to the control panel, wherein the PCB housing includes a bottom plate and a sidewall that is extended from an end portion of the bottom plate, a fastening part is provided at the sidewall of the PCB housing for the PCB to be fastened to the PCB housing, the bottom plate includes at least one hook for the PCB to be fastened to the PCB housing and the PCB includes at least one accommodating hole to accommodate the at least one hook.

Abstract: Disclosed is a data call terminating service system and method for a dynamic IP of a mobile communication terminal.

Abstract: A system and a method for releasing quality of service (QoS) resources in a mobile communication network enable QoS resources allocated to a mobile terminal to be released, if, after the mobile terminal is allocated with resources for QoS through an Evolution-Data Optimized (EVDO) Revision A (rA) network to receive data serves, the mobile terminal escapes from the EVDO rA network without first performing a resource release request to the EVDO rA network. The system and method may be implemented in the mobile terminal, the access network, the text message server, or any combination thereof, for releasing the allocated QoS resources without requiring the mobile terminal to re-connect to the EVDO rA network.

Abstract: The present invention relates to a method for forming fine wiring comprising: preparing a substrate for a printed circuit board; forming a metal thin sacrificial layer on the substrate using a first metal ink; forming a wiring on the metal thin sacrificial layer by inkjet printing using a second metal ink; and removing a portion of the metal thin sacrificial layer to form a wiring pattern. The method for forming fine wiring according to the invention can improve adhesiveness by using metal thin sacrificial layer and prevent spreading of ink in forming fine wiring.

Abstract: A method and apparatus for controlling power in a low-power multi-core system, including receiving task information from an Operation System (OS) kernel upon start and end of a task, estimating a future CPU usage using a current CPU usage in the task information, monitoring memory-related information in the task information, comparing a change in the current CPU usage with the monitored memory-related information, establishing a policy for power control based on the estimated CPU usage and the monitored memory-related information, and controlling on/off of multiple cores according to the established policy. By doing so, it is possible to solve the problems caused by performing DPM using only the CPU usage.

Abstract: A method of operating an Internet protocol (IP) address allocates, creates, and processes an interface identifier (ID) of an IP address area. In the allocation, the IP address area includes a subnet prefix area and an Interface ID area, and certain bits of the Interface ID area are used as an index area of a subnet gateway. The allocation is implemented in order from the higher layer to the lower layer so that the Interface ID area is sequentially allocated from the higher bits for the index areas of the respective layers. The combination of the certain bits of the allocated Interface ID and the subnet prefix area of the IP address area is used as the subnet ID of the subnet layers. The lowest subnet gateway allocates the Interface ID to terminating equipment to access the IP network based on a format of the IP address.

Abstract: A method of operating an Internet protocol (IP) address allocates, creates, and processes an interface identifier (ID) of an IP address area. In the allocation, the IP address area includes a subnet prefix area and an Interface ID area, and certain bits of the Interface ID area are used as an index area of a subnet gateway. The allocation is implemented in order from the higher layer to the lower layer so that the Interface ID area is sequentially allocated from the higher bits for the index areas of the respective layers. The combination of the certain bits of the allocated Interface ID and the subnet prefix area of the IP address area is used as the subnet ID of the subnet layers. The lowest subnet gateway allocates the Interface ID to terminating equipment to access the IP network based on a format of the IP address.