Abstract: The present disclosure relates to a novel salt of a 1-sulfonyl pyrrole derivative, and to a novel salt having excellent solubility in vivo, stability, bioavailability, and the like, a preparation method thereof, and a pharmaceutical composition comprising the same.

Abstract: The present invention relates to an anthracene derivative compound having a characteristic structure in which an aryl group is introduced into a skeletal structure in which deuterium-substituted phenyl and anthracene are linked. In addition, the present invention relates to a high-efficiency, long-life organic light-emitting device of which the luminous efficiency and lifetime characteristics are significantly improved by employing a polycyclic compound having a characteristic structure as a dopant for a light-emitting layer while employing said compound as a host for the light-emitting layer.

Abstract: The present invention relates to an organic light-emitting diode in which a light-emitting layer comprises a compound represented by [chemical formula A] as a host and comprises a compound represented by [chemical formula 3], [chemical formula 4], [chemical formula 3-1] to [chemical formula 4-3] as a dopant, wherein [chemical formula 3], [chemical formula 4], [chemical formula 3-1] to [chemical formula 4-3] are the same as those described in the detailed description of the invention.

Abstract: Provided is a method and apparatus for designing and testing an audio codec using quantization based on white noise modeling. A neural network-based audio encoder design method includes generating a quantized latent vector and a reconstructed signal corresponding to an input signal by using a white noise modeling-based quantization process, computing a total loss for training a neural network-based audio codec, based on the input signal, the reconstruction signal, and the quantized latent vector, training the neural network-based audio codec by using the total loss, and validating the trained neural network-based audio codec to select the best neural network-based audio codec.

Abstract: An optical path control member according to an embodiment includes a first substrate; a first electrode disposed on the first substrate; a second substrate disposed on the first substrate; a second electrode disposed under the second substrate; a light conversion unit disposed between the first electrode and the second electrode and including a plurality of accommodating parts in which a light conversion material is disposed; and a first sealing part and a second sealing part formed in a cutting region formed by cutting the second substrate, the second electrode, and the light conversion unit, and extending in a first direction, wherein the first sealing part and the second sealing part include a sealing region disposed inside the cutting region and an anchor region disposed inside the accommodating part, respectively, and wherein a size of the anchor region of the first sealing part is greater than a size of the anchor region of the second sealing part.

Abstract: The present disclosure relates to a novel salt of a 1-sulfonyl pyrrole derivative, and to a novel salt having excellent solubility in vivo, stability, bioavailability, and the like, a preparation method thereof, and a pharmaceutical composition comprising the same.

Abstract: A display device may include: a connection pattern and a dummy pattern disposed to be spaced apart from each other on a substrate; a via layer on the substrate; a pixel electrode on the via layer and electrically connected to the connection pattern; a light emitting layer disposed on the pixel electrode; a control layer disposed on the light emitting layer; and a common electrode disposed on the control layer. The dummy pattern may include a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed. The first conductive layer, the third conductive layer, and the fifth conductive layer may include the same material. The second conductive layer and the fourth conductive layer may include the same material. The first, third, fifth conductive layers and the second and fourth conductive layers may include different materials.

Abstract: The display device includes a connection pattern and a dummy pattern spaced apart from each other on a substrate; a via layer on the substrate; a pixel electrode on the via layer and electrically connected to the connection pattern; a light emitting layer on the pixel electrode; a control layer on the light emitting layer; and a common electrode on the control layer. The dummy pattern may include a first dummy pattern and a second dummy pattern disposed on the first dummy pattern. The first dummy pattern may include a first layer, a second layer, and a third layer each of which is made of a conductive material and is sequentially stacked. The second dummy pattern may include an organic pattern including a first portion and a second portion having different areas in a plan view.

Abstract: Disclosed herein are an apparatus for estimating a camera pose using multi-view images of a 2D array structure and a method using the same. The method performed by the apparatus includes acquiring multi-view images from a 2D array camera system, forming a 2D image link structure corresponding to the multi-view images in consideration of the geometric structure of the camera system, estimating an initial camera pose based on an adjacent image extracted from the 2D image link structure and a pair of corresponding feature points, and estimating a final camera pose by reconstructing a 3D structure based on the initial camera pose and performing correction so as to minimize a reprojection error of the reconstructed 3D structure.

Abstract: A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on a portion of the first epitaxial layer exposed by a trench. A second epitaxial layer is formed on the first layer. Polysilicon fills the trench to form a gate electrode. Ion-implanting impurities on the second epitaxial layer forms a source region. A second gate insulation layer is formed on the gate electrode and the gate oxide layer, a source silicide is formed on the second gate insulation layer, and an interlayer insulation layer is formed on the second epitaxial layer, source region and source silicide. Source, gate and drain contact holes expose the source silicide, gate electrode and drain silicide.

Abstract: A method of manufacturing a semiconductor device providing insulation between a plurality of MOS transistors without device isolation regions. The method includes forming a first insulation layer on a substrate, exposing a portion of the substrate by etching the first insulation layer using a resist, growing an epitaxial layer on the exposed portion of the substrate, removing the patterned first insulation layer, and forming transistors on the substrate and epitaxial layer, respectively. The epitaxial layer is grown to a degree that an upper surface of the epitaxial layer is higher than that of the substrate.

Abstract: A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on a portion of the first epitaxial layer exposed by a trench. A second epitaxial layer is formed on the first layer. Polysilicon fills the trench to form a gate electrode. Ion-implanting impurities on the second epitaxial layer forms a source region. A second gate insulation layer is formed on the gate electrode and the gate oxide layer, a source silicide is formed on the second gate insulation layer, and an interlayer insulation layer is formed on the second epitaxial layer, source region and source silicide. Source, gate and drain contact holes expose the source silicide, gate electrode and drain silicide.

Abstract: A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on a portion of the first epitaxial layer exposed by a trench. A second epitaxial layer is formed on the first layer. Polysilicon fills the trench to form a gate electrode. Ion-implanting impurities on the second epitaxial layer forms a source region. A second gate insulation layer is formed on the gate electrode and the gate oxide layer, a source silicide is formed on the second gate insulation layer, and an interlayer insulation layer is formed on the second epitaxial layer, source region and source silicide. Source, gate and drain contact holes expose the source silicide, gate electrode and drain silicide.

Abstract: A method of manufacturing a semiconductor device providing insulation between a plurality of MOS transistors without device isolation regions. The method includes forming a first insulation layer on a substrate, exposing a portion of the substrate by etching the first insulation layer using a resist, growing an epitaxial layer on the exposed portion of the substrate, removing the patterned first insulation layer, and forming transistors on the substrate and epitaxial layer, respectively. The epitaxial layer is grown to a degree that an upper surface of the epitaxial layer is higher than that of the substrate.

Abstract: A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on a portion of the first epitaxial layer exposed by a trench. A second epitaxial layer is formed on the first layer. Polysilicon fills the trench to form a gate electrode. Ion-implanting impurities on the second epitaxial layer forms a source region. A second gate insulation layer is formed on the gate electrode and the gate oxide layer, a source silicide is formed on the second gate insulation layer, and an interlayer insulation layer is formed on the second epitaxial layer, source region and source silicide. Source, gate and drain contact holes expose the source silicide, gate electrode and drain silicide.