Patents by Inventor Joon-Jin Park
Joon-Jin Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240164206Abstract: The present invention relates to: a pyrene derivative compound having a specific structure; and a high efficiency organic light-emitting device employing the pyrene derivative compound in a light emitting layer and thus having excellent light-emitting characteristics. The organic light-emitting device according to the present invention can be configured as a high efficiency organic light-emitting device having excellent light-emitting characteristics by employing the pyrene derivative compound having the specific structure as a host in the light emitting layer, and thus can be usefully applied industrially in lighting devices, as well as various display devices such as flat, flexible, and wearable displays.Type: ApplicationFiled: February 15, 2022Publication date: May 16, 2024Inventors: Se-jin LEE, Si-in KIM, Seok-bae PARK, Hee-dae KIM, Yeong-tae CHOI, Seung-soo LEE, Ji-yung KIM, Kyeong-hyeon KIM, Kyung-tae KIM, Myeong-jun KIM, Tae-gyun LEE, Joon-ho KIM
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Publication number: 20240164177Abstract: A display device includes a pixel electrode, a pixel defining layer including an opening extending to a portion of the pixel electrode, a first auxiliary electrode on the portion of the pixel electrode to which the opening extends, a second auxiliary electrode on the first auxiliary electrode, an intermediate layer on the pixel defining layer and the second auxiliary electrode, and a common electrode on the intermediate layer. A side surface of the first auxiliary electrode is positioned inward of a side surface of the second auxiliary electrode within the opening of the pixel defining layer to form an undercut shape. A hole injection layer of the intermediate layer includes a first portion on a side surface of the pixel defining layer defining the opening of the pixel defining layer, and a second portion disconnected from the first portion and on the second auxiliary electrode.Type: ApplicationFiled: August 9, 2023Publication date: May 16, 2024Inventors: Jae Ik KIM, Hye Jin GWARK, Hwi KIM, Jung Sun PARK, Yeon Hwa LEE, Joon Gu LEE
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Publication number: 20240155938Abstract: An organic light-emitting device according to the present invention uses a pyrene derivative compound having a characteristic structure as a host in a light-emitting layer to realize a long-lifespan and high-efficiency organic light-emitting device having excellent light-emitting characteristics in terms of lifespan and luminescence efficiency. Accordingly, the organic light-emitting device can be usefully applied, in the industrial aspect, for various display devices such as flat panel, flexible, and wearable displays, as well as lighting devices.Type: ApplicationFiled: February 15, 2022Publication date: May 9, 2024Inventors: Se-jin LEE, Si-in KIM, Seok-bae PARK, Hee-dae KIM, Yeong-tae CHOI, Seung-soo LEE, Ji-yung KIM, Kyeong-hyeon KIM, Kyung-tae KIM, Myeong-jun KIM, Tae-gyun LEE, Joon-ho KIM
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Publication number: 20240107857Abstract: A display device includes a thin-film transistor, a source/drain electrode and an auxiliary electrode including a first conductive layer and a second conductive layer disposed on the first conductive layer, a via insulating layer having a first opening exposing the auxiliary electrode, a capping layer covering a portion of the auxiliary electrode and a light emitting material layer and a common electrode layer sequentially stacked on the via insulating layer and the capping layer, wherein the source/drain electrode is electrically connected to the thin-film transistor through a contact hole penetrating the interlayer insulating layer, the auxiliary electrode has an undercut, and the capping layer includes a first capping layer covering side surfaces of the first conductive layer of the auxiliary electrode and a second capping layer separated from the first capping layer and disposed on the second conductive layer of the auxiliary electrode.Type: ApplicationFiled: June 20, 2023Publication date: March 28, 2024Applicant: Samsung Display Co., LTD.Inventors: Joon Gu LEE, Hye Jin GWARK, Jae Ik KIM, Hwi KIM, Jung Sun PARK, Yeon Hwa LEE
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Patent number: 11942488Abstract: A display device includes: a substrate; a first conductive layer on the substrate and comprising a first signal line; an insulating layer pattern on the first conductive layer; a semiconductor pattern on the insulating layer pattern; a gate insulating layer on the semiconductor pattern; and a second conductive layer comprising a gate electrode on the gate insulting layer and a first source/drain electrode and a second source/drain electrode, each on at least a part of the semiconductor pattern, wherein the insulating layer pattern and the semiconductor pattern have a same planar shape, the semiconductor pattern comprises a channel region overlapping the gate electrode, a first source/drain region on a first side of the channel region and a second source/drain region on a second side of the channel region, and the first source/drain electrode electrically connects the first source/drain region and the first signal line.Type: GrantFiled: March 30, 2023Date of Patent: March 26, 2024Assignee: Samsung Display Co., Ltd.Inventors: Kyung Jin Jeon, So Young Koo, Eok Su Kim, Hyung Jun Kim, Joon Seok Park, Jun Hyung Lim
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Publication number: 20240090318Abstract: The present invention relates to a novel heterocyclic compound usable in an organic light-emitting device and to an organic light-emitting device comprising same, wherein [chemical formula A] is as described in the detailed description of the invention.Type: ApplicationFiled: December 28, 2021Publication date: March 14, 2024Inventors: Se-Jin LEE, Seok-Bae PARK, Si-In KIM, Hee-Dae KIM, Yeong-Tae CHOI, Ji-Yung KIM, Kyung-Tae KIM, Myeong-Jun KIM, Kyeong-hyeon KIM, Seung-soo LEE, Tae Gyun LEE, Joon-Ho KIM
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Publication number: 20240086603Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Applicant: SAMSUNG ELECTRONICS CO, LTD.Inventors: In HUH, Jeong-hoon KO, Hyo-jin CHOI, Seung-ju KIM, Chang-wook JEONG, Joon-wan CHAI, Kwang-II PARK, Youn-sik PARK, Hyun-sun PARK, Young-min OH, Jun-haeng LEE, Tae-ho LEE
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Patent number: 11923216Abstract: An apparatus and method for treating a substrate are provided. The apparatus includes at least one first process chamber configured to supply a developer onto the substrate; at least one second process chamber configured to treat the substrate using a supercritical fluid; a transfer chamber configured to transfer the substrate from the at least one first process chamber to the at least one second process chamber, while the developer supplied in the at least one first process chamber remains on the substrate; and a temperature and humidity control system configured to manage temperature and humidity of the transfer chamber by supplying a first gas of constant temperature and humidity into the transfer chamber.Type: GrantFiled: August 22, 2022Date of Patent: March 5, 2024Assignees: SAMSUNG ELECTRONICS CO., LTD., SEMES CO., LTD.Inventors: Seung Min Shin, Sang Jin Park, Hae Won Choi, Jang Jin Lee, Ji Hwan Park, Kun Tack Lee, Koriakin Anton, Joon Ho Won, Jin Yeong Sung, Pil Kyun Heo
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Patent number: 11919122Abstract: A substrate processing apparatus includes: a conveyor belt configured to have an outer surface on which a bottom surface of a substrate is seated; and a polishing head unit configured to face an upper surface of the substrate, wherein the polishing head unit includes: a polishing head connected to a driver; a polishing pad configured to face the polishing head; a polishing pad fixing ring disposed between the polishing head and the polishing pad; and a temperature sensor configured to overlap the polishing pad fixing ring and to be spaced apart from the polishing pad fixing ring.Type: GrantFiled: September 29, 2020Date of Patent: March 5, 2024Assignees: SAMSUNG DISPLAY CO., LTD., KCTECH CO., LTD.Inventors: Seung Bae Kang, Sung Hyeon Park, Jung Gun Nam, Joon-Hwa Bae, Kyung Bo Lee, Keun Woo Lee, Woo Jin Cho, Byoung Kwon Choo
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Patent number: 7701000Abstract: A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on a portion of the first epitaxial layer exposed by a trench. A second epitaxial layer is formed on the first layer. Polysilicon fills the trench to form a gate electrode. Ion-implanting impurities on the second epitaxial layer forms a source region. A second gate insulation layer is formed on the gate electrode and the gate oxide layer, a source silicide is formed on the second gate insulation layer, and an interlayer insulation layer is formed on the second epitaxial layer, source region and source silicide. Source, gate and drain contact holes expose the source silicide, gate electrode and drain silicide.Type: GrantFiled: July 22, 2008Date of Patent: April 20, 2010Assignee: Dongbu Electronics Co., Ltd.Inventor: Joon-Jin Park
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Patent number: 7521302Abstract: A method of manufacturing a semiconductor device providing insulation between a plurality of MOS transistors without device isolation regions. The method includes forming a first insulation layer on a substrate, exposing a portion of the substrate by etching the first insulation layer using a resist, growing an epitaxial layer on the exposed portion of the substrate, removing the patterned first insulation layer, and forming transistors on the substrate and epitaxial layer, respectively. The epitaxial layer is grown to a degree that an upper surface of the epitaxial layer is higher than that of the substrate.Type: GrantFiled: December 30, 2005Date of Patent: April 21, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Joon-Jin Park
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Publication number: 20080277722Abstract: A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on a portion of the first epitaxial layer exposed by a trench. A second epitaxial layer is formed on the first layer. Polysilicon fills the trench to form a gate electrode. Ion-implanting impurities on the second epitaxial layer forms a source region. A second gate insulation layer is formed on the gate electrode and the gate oxide layer, a source silicide is formed on the second gate insulation layer, and an interlayer insulation layer is formed on the second epitaxial layer, source region and source silicide. Source, gate and drain contact holes expose the source silicide, gate electrode and drain silicide.Type: ApplicationFiled: July 22, 2008Publication date: November 13, 2008Inventor: Joon-Jin Park
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Patent number: 7416946Abstract: A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on a portion of the first epitaxial layer exposed by a trench. A second epitaxial layer is formed on the first layer. Polysilicon fills the trench to form a gate electrode. Ion-implanting impurities on the second epitaxial layer forms a source region. A second gate insulation layer is formed on the gate electrode and the gate oxide layer, a source silicide is formed on the second gate insulation layer, and an interlayer insulation layer is formed on the second epitaxial layer, source region and source silicide. Source, gate and drain contact holes expose the source silicide, gate electrode and drain silicide.Type: GrantFiled: December 23, 2005Date of Patent: August 26, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Joon-Jin Park
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Publication number: 20060148144Abstract: A method of manufacturing a semiconductor device providing insulation between a plurality of MOS transistors without device isolation regions. The method includes forming a first insulation layer on a substrate, exposing a portion of the substrate by etching the first insulation layer using a resist, growing an epitaxial layer on the exposed portion of the substrate, removing the patterned first insulation layer, and forming transistors on the substrate and epitaxial layer, respectively. The epitaxial layer is grown to a degree that an upper surface of the epitaxial layer is higher than that of the substrate.Type: ApplicationFiled: December 30, 2005Publication date: July 6, 2006Applicant: DongbuAnam Semiconductor Inc.Inventor: Joon-Jin Park
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Publication number: 20060141689Abstract: A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on a portion of the first epitaxial layer exposed by a trench. A second epitaxial layer is formed on the first layer. Polysilicon fills the trench to form a gate electrode. Ion-implanting impurities on the second epitaxial layer forms a source region. A second gate insulation layer is formed on the gate electrode and the gate oxide layer, a source silicide is formed on the second gate insulation layer, and an interlayer insulation layer is formed on the second epitaxial layer, source region and source silicide. Source, gate and drain contact holes expose the source silicide, gate electrode and drain silicide.Type: ApplicationFiled: December 23, 2005Publication date: June 29, 2006Applicant: DongbuAnam Semiconductor Inc.Inventor: Joon-Jin Park