Abstract: The present invention relates to a decoding method of a software modem in a limited memory environment using overlapping fragmentation and progressive decoding, which processes packets in real-time and reduces power consumption in an environment in which memory is limited when the software modem is used, and the decoding method includes: (a) receiving a data packet from the signal processing device, by the software modem; (b) fragmenting the data packet, decoding the fragments by the fragment, and transferring a decoded MAC header to the MAC module, by the software modem; (c) analyzing the MAC header and verifying whether the packet is a data packet transmitted to the MAC module itself or the packet is damaged, by the MAC module; (d) directing, when the data packet is verified, the software modem to perform additional decoding on the data packet, by the MAC module; and (e) directing, when the data packet is not verified, the software modem to drop the data packet, by the MAC module.

Abstract: A touch window includes a substrate including an available area and an unavailable area; and an electrode layer formed on the substrate, wherein the electrode layer includes a conductive layer and a protective layer formed on the conductive layer, the protective layer is in direct contact with the conductive layer, the protective layer has a thickness different from that of the conductive layer, and the protective layer includes a black-based color.

Abstract: A touch window includes a substrate including an available area and an unavailable area; and an electrode layer formed on the substrate, wherein the electrode layer includes a conductive layer and a protective layer formed on the conductive layer, the protective layer is in direct contact with the conductive layer, the protective layer has a thickness different from that of the conductive layer, and the protective layer includes a black-based color.

Abstract: A semiconductor package includes: first, second, third and fourth semiconductor chips stacked while having the arrangement of chip selection vias; and a connection unit provided between a second semiconductor chip and a third semiconductor chip, and configured to mutually connect some of the chip selection vias of the second and third semiconductor chips and disconnect the others of the chip selection vias of the second and third semiconductor chips, wherein the first and second semiconductor chips and the third and fourth semiconductor chips are stacked in a flip chip type.

Abstract: A semiconductor package includes: first, second, third and fourth semiconductor chips stacked while having the arrangement of chip selection vias; and a connection unit provided between a second semiconductor chip and a third semiconductor chip, and configured to mutually connect some of the chip selection vias of the second and third semiconductor chips and disconnect the others of the chip selection vias of the second and third semiconductor chips, wherein the first and second semiconductor chips and the third and fourth semiconductor chips are stacked in a flip chip type.

Abstract: A stack chip module includes a substrate having a predetermined-size groove on one side and a circuit pattern, one end of the circuit pattern being adjacent to the groove; a first semiconductor chip adhered in the groove of the substrate by adhesive and having a plurality of center pads and a plurality of edge pads, electrically connected to each other, on the upper part thereof; a plurality of gold wires for electrically connecting the circuit pattern of the substrate and the edge pads of the first semiconductor chip, respectively; a second semiconductor chip having a plurality of center pads corresponding to those of the first semiconductor chip, the formative side being opposite to that of the first semiconductor chip; and a plurality of bumps interposed between the center pads of the first semiconductor chip and the center pads of the second semiconductor chip for joining and electrically connecting them.

Abstract: A stack chip module includes a substrate having a predetermined-size groove on one side and a circuit pattern, one end of the circuit pattern being adjacent to the groove; a first semiconductor chip adhered in the groove of the substrate by adhesive and having a plurality of center pads and a plurality of edge pads, electrically connected to each other, on the upper part thereof; a plurality of gold wires for electrically connecting the circuit pattern of the substrate and the edge pads of the first semiconductor chip, respectively; a second semiconductor chip having a plurality of center pads corresponding to those of the first semiconductor chip, the formative side being opposite to that of the first semiconductor chip; and a plurality of bumps interposed between the center pads of the first semiconductor chip and the center pads of the second semiconductor chip for joining and electrically connecting them.

Abstract: A structure of a stackable semiconductor package, includes a stacked semiconductor package in which a plurality of semiconductor packages are stacked, each semiconductor package having a plurality of external leads at side surfaces thereof, and conductive wires for electrically connecting the corresponding external leads of said semiconductor packages of said stacked semiconductor package. The stacked structure of stackable semiconductor packages and the method of stacking the same improves the productivity by using an automatic wiring technique for electrically connecting the corresponding external leads. In addition, since the thickness of each wire which is used for lastly transmitting signals can be adjusted, the flexibility thereof increases and thereby the reliability can be improved in the solder joint.

Abstract: A lead frame and a semiconductor chip package includes supporters on a lead frame paddle and tiebars using the same for preventing undesired paddle bending which may occur due to the pressure of an epoxy molding compound during the molding process. The supports also allow improved heat dissipation during the molding process of the semiconductor chip package and mounting process of the package onto a printed circuit board.

Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads on its top surface, a plurality of inner leads located above the semiconductor chip and electrically connected to the bonding pads by wire, a plurality of outer leads extending from the respective inner leads, and at least one bus bar formed lower than the inner leads, to prevent electrical shorts and improve reliability of the package.

Abstract: An improved device for mounting a semiconductor package when testing electrical characteristics of the semiconductor package is capable of reducing stress which is applied to the semiconductor package. The device includes a shaped body, a plurality of spaced-apart protrusions that vertically extend from a first pair of opposing upper sides of the body, a plurality of guide blocks that extend from a second pair of opposing upper sides of the body, and a plurality of leads that extend from the top surface of the body and down side surfaces of the body. The leads may include inner portions that extend inward from the first pair of opposing upper sides of the body, and outer portions that extend down the sides of the body. In addition, a plurality of guide hooks for holding a semiconductor package may be formed on upper surfaces of the protrusions and/or the guide blocks.

Abstract: A semiconductor package is disclosed including a semiconductor chip having a plurality of bonding pads on its top surface; a plurality of inner leads located above the semiconductor chip and electrically connected to the bonding pads by wire; a plurality of outer leads extending from the respective inner leads; and at least one bus bar for power supply and ground formed to be lower than the inner leads above the semiconductor chip. A method of packaging a semiconductor device is disclosed including the steps of: providing a semiconductor chip having a plurality of bonding pads on its top surface; arranging a plurality of inner leads and a plurality of outer leads extending therefrom above the semiconductor chip; and arranging bus bars for power supply and ground to be lower than the inner leads above the semiconductor chip.