Abstract: Security processing circuits are discussed which may be used alone or as part of a network interface device of a host system using a single DES engine to accomplish 3DES processing. The security processing circuit is adapted for selectively encrypting outgoing data and decrypting incoming data, where the network interface device may be fabricated as a single integrated circuit chip. Methods are also provided for performing 3DES encryption and decryption services between the host system and a network, in which security information is obtained from the host system, which is used together with a set of secret keys for 3DES processing data utilizing a single DES engine and an intermediate result fed back to the single DES engine of the 3DES IPsec circuit.

Abstract: Improved security processing circuits are discussed which may be used alone or as part of a network interface device of a host system using a DES engine to accomplish 3DES processing. The security processing circuit is adapted for selectively encrypting outgoing data and decrypting incoming data, where the network interface device may be fabricated as a single integrated circuit chip. The improved circuit makes use of a unique circuit component arrangement to provide shortened path timings within the DES engine processing. To accomplish this overall timing performance improvement, the permutation and inverse permutation blocks are removed from these critical path timings of the three individual DES processing operations, and moved to the beginning and end of the 3DES process.

Abstract: A method and apparatus for automatically verifying whether a network interface is transmitting frame data properly. Frame data stored in host memory is transmitted to the network interface and to a transmit data checker. The network interface receives, processes and transmits the frame data. The processed frame data is transmitted to a network media and to the transmit data checker. The transmit data checker compares the frame data from the host memory with the processed frame data from the network interface and generates an indicator signal. The indicator signal indicates whether the network interface is transmitting processed frame data properly. The indicator signal is sent to a display which displays the result. The transmit data checker includes a timer for determining the processing time of the network interface. The timer measures the time between reception of the frame data from the host memory and the reception of the transmitted data.

Abstract: A method for testing and verifying an integrated circuit using a bottom-up approach to generate a complete integrated circuit. The design for an integrated circuit is divided or defined into individual sub-system modules which are then tested either individually or as a combination of sub-system modules (e.g., a partially integrated circuit). Once all of the sub-system modules are tested and verified, the sub-system modules can be combined to form a complete integrated circuit which can then be tested. Each of the sub-system modules, the partially integrated circuit and the complete integrated circuit are tested and verified.