Abstract: A memory system includes a memory controller configured to control an operation of a memory cell array through a first command/address pin and a second other command/address pin and a memory device. The memory device includes a plurality of data pins configured to exchange data input with the memory cell array according to a command/address provided through the first and second command/address pins to the memory controller, a first flip-flop to sample a first command/address signal provided through the first command/address pin as first command/address data at a first time, and a second flip-flop to sample a second command/address signal provided through the second command/address pin as second command/address data at the first time. The memory device provides the first and second command/address data to the memory controller through a first data pin among the plurality of data pins.

Abstract: A memory system includes a memory controller configured to control an operation of a memory cell array through a first command/address pin and a second other command/address pin and a memory device. The memory device includes a plurality of data pins configured to exchange data input with the memory cell array according to a command/address provided through the first and second command/address pins to the memory controller, a first flip-flop to sample a first command/address signal provided through the first command/address pin as first command/address data at a first time, and a second flip-flop to sample a second command/address signal provided through the second command/address pin as second command/address data at the first time. The memory device provides the first and second command/address data to the memory controller through a first data pin among the plurality of data pins.

Abstract: A memory controller includes a memory capacity setting circuit and an address selecting circuit. The memory capacity setting circuit is configured to set a valid memory capacity of a memory device based on a defective cell information signal, and generate a valid memory capacity signal based on the valid memory capacity. The address selecting circuit is configured to disable an address signal corresponding to a memory block having a defective cell, and generate a selection address signal based on the valid memory capacity signal and the disabled address signal. A non-defective cell in a memory cell array is activated based on the selection address signal and a command signal.

Abstract: Semiconductor memory devices are provided. The semiconductor memory device includes a command decoder, a code converter and a code outputting unit. The command decoder is configured to receive a plurality of command signals from an external source, decode the plurality of command signals and generate a mode register reading signal responsive to the decoded plurality of command signals. The code converter is configured to receive mode setting codes generated based on the decoded plurality of command signals and convert the mode setting codes to serial mode setting codes. The code outputting unit is configured to receive the serial mode setting codes and output the serial mode setting codes to the external source responsive to the mode register reading signal. Systems including the semiconductor memory devices are also provided.

Abstract: Semiconductor memory devices are provided. The semiconductor memory device includes a command decoder, a code converter and a code outputting unit. The command decoder is configured to receive a plurality of command signals from an external source, decode the plurality of command signals and generate a mode register reading signal responsive to the decoded plurality of command signals. The code converter is configured to receive mode setting codes generated based on the decoded plurality of command signals and convert the mode setting codes to serial mode setting codes. The code outputting unit is configured to receive the serial mode setting codes and output the serial mode setting codes to the external source responsive to the mode register reading signal. Systems including the semiconductor memory devices are also provided.