Abstract: A carrier head for a chemical mechanical polishing apparatus is provided. The carrier head includes a base and a substrate receiving member connected to a lower part of the base. Inside of the substrate receiving member, at least one contact flap is connected to the lower part of the base. The at least one contact flap includes a connecting portion, a side portion extended downwardly from the connecting portion and a contact portion extended sidewardly from a bottom end of the side portion. Adjacent to the at least one contact flap, at least one wall structure is connected to the lower part of the base to limit an expansion of the at least one contact flap for a firm contact of the contact portion with an inner surface of the substrate receiving member by means of fluid pressure.

Abstract: A carrier head for a chemical mechanical polishing apparatus comprises: a base; a substrate receiving member comprising a plate portion having an outer surface for receiving a substrate and an inner surface at the back of the outer surface, a perimeter portion extended in a height direction from an edge of the plate portion, a securing portion extended from an outer part of the perimeter portion and connected to a lower part of the base, and a contact portion extended from an inner part of the perimeter portion; a contact coupling structure connected to the lower part of the base to provide a contact surface to the contact portion; and a perimeter portion pressurizing chamber formed by taking the securing portion and the contact portion as chamber walls when the contact portion contacts firmly the contact coupling structure by means of fluid pressure.

Abstract: Disclosed herein is a carrier head for a chemical mechanical polishing system. The carrier head for a chemical mechanical polishing system includes a base. A substrate receiving member having an outer surface against which a substrate can be mounted is connected to a lower part of the base. Inside of the substrate receiving member, at least two bladders are connected to the lower part of the base. The at least two bladders can apply pressure independently to predetermined areas of an inner surface of the substrate receiving member by expanding and contacting the inner surface. At least one wall structure is connected to the lower part of the base, wherein the at least one wall structure can limit lateral expansions of the at least two bladders.

Abstract: One or more embodiments of the instant invention may be briefly summarized as follows. A planarization and smoothing segment includes: (a) a reverse mask and etching method; a sacrificial layer and selective CMP followed by non selective CMP; or a sacrificial layer and selective etching followed by non-selective CMP. A buffer layer to protect wave guide segment includes: (a) waveguide formation followed by buffer layer deposition; or a buffer deposition over the waveguide layer followed by waveguide formation.

Abstract: One or more embodiments of the instant invention may be briefly summarized as follows. A planarization and smoothing segment includes: (a) a reverse mask and etching method; a sacrificial layer and selective CMP followed by non selective CMP; or a sacrificial layer and selective etching followed by non-selective CMP. A buffer layer to protect wave guide segment includes: (a) waveguide formation followed by buffer layer deposition; or a buffer deposition over the waveguide layer followed by waveguide formation.

Abstract: A method is described for reducing dishing in a chemical mechanical polishing process performed on a semiconductor wafer having a dielectric layer with trenches and a copper layer deposited over the dielectric layer and filling the trenches in the dielectric layer. The method comprises steps of removing excess copper above the plane of the dielectric surface using a main polishing operation, whereby copper residues are formed above the plane of the dielectric surface, and applying chemical treatment to the surface of the semiconductor wafer in the initial stage of an overpolishing operation, wherein a protective layer over the copper residues and surfaces of copper-filled trenches is formed. The method further comprises steps of removing the copper residues and protective layer thereon above the plane of the dielectric layer in the overpolishing operation, and removing the protective layer over the surfaces of the copper-filled trenches in the overpolishing operation.

Abstract: A method is described for reducing dishing in a chemical mechanical polishing process performed on a semiconductor wafer having a dielectric layer with trenches and a copper layer deposited over the dielectric layer and filling the trenches in the dielectric layer. The method comprises steps of removing excess copper above the plane of the dielectric surface using a main polishing operation, whereby copper residues are formed above the plane of the dielectric surface, and applying chemical treatment to the surface of the semiconductor wafer in the initial stage of an overpolishing operation, wherein a protective layer over the copper residues and surfaces of copper-filled trenches is formed. The method further comprises steps of removing the copper residues and protective layer thereon above the plane of the dielectric layer in the overpolishing operation, and removing the protective layer over the surfaces of the copper-filled trenches in the overpolishing operation.

Abstract: Disclosed is a method of forming quantum wires for compound semiconductors capable of forming a large number of quantum wires. Quantum wires for compound semiconductors according to the present invention are formed by the following processes. First, a compound semiconductor substrate is provided and Al.sub.X Ga.sub.1-X As layers and GaAs layers are then formed alternately on the substrate to predetermined times to form a quantum well. Next, a plurality of grooves are formed in the upper most GaAs layer to a predetermined depth wherein the grooves are separated with a predetermined space from each other. Stress is applied to the quantum well such that the Al.sub.X Ga.sub.1-X As layers surround the GaAs layers to thereby form a large number of quantum wires.