Patents by Inventor Joon-mo Kwon
Joon-mo Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210358917Abstract: A method of producing a semiconductor memory device includes following operations. A substrate is provided. A stacked structure is formed on the substrate. Capacitor holes arranged at intervals are formed in the stacked structure. Bottom electrode layers are formed in the capacitor holes. A top-layer dielectric layer is removed. A first capacitor dielectric layer is formed on exposed surfaces of a sacrificial layer and surfaces of upper parts of the bottom electrode layers. A first top electrode layer is formed on a surface of the first capacitor dielectric layer. Multiple openings are formed in the first top electrode layer and first capacitor dielectric layer. The sacrificial layer is removed through the openings. A second capacitor dielectric layer is formed. A second top electrode layer is formed on a surface of the second capacitor dielectric layer.Type: ApplicationFiled: July 27, 2021Publication date: November 18, 2021Inventor: JOON MO KWON
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Patent number: 7825496Abstract: A semiconductor device includes an interlayer insulating layer on a semiconductor substrate, at least one plug on the semiconductor substrate, the plug extending through the interlayer insulating layer toward an upper portion of the semiconductor substrate, the plug having a lower part with a first diameter and an upper part with a second diameter different from the first diameter, a filling pattern on the interlayer insulating layer, the filling pattern surrounding the upper part of the plug, and an upper surface of the filling pattern being substantially coplanar with an upper surface of the plug, the upper surface of the plug facing away from the semiconductor substrate, and a protection pattern on the upper part of the plug, the protection pattern being between the plug, the filling pattern, and the interlayer insulating layer.Type: GrantFiled: November 24, 2008Date of Patent: November 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Wan Ma, Joon-Mo Kwon
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Publication number: 20090134525Abstract: A semiconductor device includes an interlayer insulating layer on a semiconductor substrate, at least one plug on the semiconductor substrate, the plug extending through the interlayer insulating layer toward an upper portion of the semiconductor substrate, the plug having a lower part with a first diameter and an upper part with a second diameter different from the first diameter, a filling pattern on the interlayer insulating layer, the filling pattern surrounding the upper part of the plug, and an upper surface of the filling pattern being substantially coplanar with an upper surface of the plug, the upper surface of the plug facing away from the semiconductor substrate, and a protection pattern on the upper part of the plug, the protection pattern being between the plug, the filling pattern, and the interlayer insulating layer.Type: ApplicationFiled: November 24, 2008Publication date: May 28, 2009Inventors: Jong-Wan Ma, Joon-Mo Kwon
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Patent number: 7192822Abstract: According to some embodiments, methods of fabricating a complementary metal oxide semiconductor (CMOS) type semiconductor device having dual gates are provided. The method includes forming an insulated first gate electrode on the P-type well, and an insulated second initial gate electrode on the N-type well. A first lower interlayer insulating layer exposing a top surface of the first gate electrode is formed on the P-type well while a second lower interlayer insulating layer exposing a top surface of the second initial gate electrode is formed on the N-type well. P-type impurity ions are selectively implanted into the second initial gate electrode to form a second gate electrode. A first ion implantation mask pattern is formed over the first gate electrode while a second ion implantation mask pattern is formed over the second gate electrode. The second lower interlayer insulating layer is etched, using the second ion implantation mask pattern as an etch mask, to expose a top surface of the N-type well.Type: GrantFiled: September 13, 2005Date of Patent: March 20, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Jun Park, Joon-Mo Kwon
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Patent number: 7148116Abstract: A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.Type: GrantFiled: June 30, 2005Date of Patent: December 12, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Won Shik Lee, Joon-Mo Kwon, Tae Kyung Kim, Jin-Kee Choi, Dong-Gun Park, Hyeong-Chan Ko, Hong-Joon Moon
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Publication number: 20060255391Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.Type: ApplicationFiled: July 24, 2006Publication date: November 16, 2006Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Beom KIM, Won-Mo PARK, Yun-Jae LEE, Joon-Mo KWON, Myoung-Hee HAN, Man-Jong YU
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Patent number: 7101769Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.Type: GrantFiled: February 10, 2004Date of Patent: September 5, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Beom Kim, Won-Mo Park, Yun-Jae Lee, Joon-Mo Kwon, Myoung-Hee Han, Man-Jong Yu
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Patent number: 7084478Abstract: A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.Type: GrantFiled: October 16, 2002Date of Patent: August 1, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Won Shik Lee, Joon-Mo Kwon, Tae Kyung Kim, Jin-Kee Choi, Dong-Gun Park, Hyeong-Chan Ko, Hong-Joon Moon
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Publication number: 20060068539Abstract: According to some embodiments, methods of fabricating a complementary metal oxide semiconductor (CMOS) type semiconductor device having dual gates are provided. The method includes forming an insulated first gate electrode on the P-type well, and an insulated second initial gate electrode on the N-type well. A first lower interlayer insulating layer exposing a top surface of the first gate electrode is formed on the P-type well while a second lower interlayer insulating layer exposing a top surface of the second initial gate electrode is formed on the N-type well. P-type impurity ions are selectively implanted into the second initial gate electrode to form a second gate electrode. A first ion implantation mask pattern is formed over the first gate electrode while a second ion implantation mask pattern is formed over the second gate electrode. The second lower interlayer insulating layer is etched, using the second ion implantation mask pattern as an etch mask, to expose a top surface of the N-type well.Type: ApplicationFiled: September 13, 2005Publication date: March 30, 2006Inventors: Byung-Jun Park, Joon-Mo Kwon
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Publication number: 20050255662Abstract: A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.Type: ApplicationFiled: June 30, 2005Publication date: November 17, 2005Inventors: Won Lee, Joon-Mo Kwon, Tae Kim, Jin-Kee Choi, Dong-Gun Park, Hyeong-Chan Ko, Hong-Joon Moon
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Publication number: 20050218448Abstract: A transistor structure and a method of forming the same prevent a boundary face of first and second gate electrodes from being oxidized in a subsequent oxidation process, by forming an oxidation inhibition layer in the boundary face. A gate insulation layer is formed on a semiconductor substrate, and a gate stack is obtained by a sequential accumulation of first and second gate electrodes and a capping layer on the gate insulation layer. An oxidation inhibition layer is formed in a sidewall portion of the gate stack, and the oxidation inhibition layer covers a boundary face of the first and second gate electrodes. Source/drain regions are opposite to the gate stack.Type: ApplicationFiled: March 18, 2005Publication date: October 6, 2005Inventors: Dae-Ik Kim, Joon-Mo Kwon, Byung-Hak Lee
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Publication number: 20040159909Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.Type: ApplicationFiled: February 10, 2004Publication date: August 19, 2004Inventors: Seung-Beom Kim, Won-Mo Park, Yun-Jae Lee, Joon-Mo Kwon, Myoung-Hee Han, Man-Jong Yu
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Publication number: 20030178697Abstract: A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.Type: ApplicationFiled: October 16, 2002Publication date: September 25, 2003Inventors: Won Shik Lee, Joon-Mo Kwon, Tae Kyung Kim, Jin-Kee Choi, Dong-Gun Park, Hyeong-Chan Ko, Hong-Joon Moon
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Patent number: 6271105Abstract: A method is provided for forming a multiple well of a semiconductor device is provided. By this method, a pocket well region of a first conductivity type is formed over a predetermined first region of a semiconductor substrate of a first conductivity type, using a first photolithography process. A first deep well region of a second conductivity type is then formed under the pocket well region in a self-aligned manner. A peripheral well region of the first conductivity type is selectively formed in a predetermined second region of the semiconductor substrate apart from the pocket well region, using a second photolithography process.Type: GrantFiled: May 21, 1999Date of Patent: August 7, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-mo Kwon, Sung-young Lee