Patents by Inventor Joon-myoung LEE

Joon-myoung LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS OF MANUFACTURING MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES
    Publication number: 20150207064
    Abstract: A MRAM device may include a fixed layer pattern on a substrate, a first tunnel barrier layer pattern on the fixed layer pattern, a free layer pattern on the first tunnel barrier layer pattern, a second tunnel barrier layer pattern on the free layer pattern, the second tunnel barrier layer pattern including a metal oxide, and a capping layer pattern on the second tunnel barrier layer pattern. The capping layer pattern including a metal may have an oxide layer formation energy lower than the oxide layer formation energy of tantalum.
    Type: Application
    Filed: October 3, 2014
    Publication date: July 23, 2015
    Inventors: Joon-Myoung LEE, Hong-Lae PARK, Sang-Yong KIM, Woo-Chang LIM
  • Semiconductor device having pinned layer with enhanced thermal endurance
    Patent number: 9087977
    Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: July 21, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Heon Park, Ki-Woong Kim, Hee-Ju Shin, Joon-Myoung Lee, Woo-Jin Kim, Jae-Hoon Kim, Se-Chung Oh, Yun-Jae Lee
  • SEMICONDUCTOR DEVICE HAVING PINNED LAYER WITH ENHANCED THERMAL ENDURANCE
    Publication number: 20150048464
    Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.
    Type: Application
    Filed: April 16, 2014
    Publication date: February 19, 2015
    Inventors: JEONG-HEON PARK, KI-WOONG KIM, HEE-JU SHIN, JOON-MYOUNG LEE, WOO-JIN KIM, JAE-HOON KIM, SE-CHUNG OH, YUN-JAE LEE
  • MAGNETIC DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20140021426
    Abstract: A magnetic device comprises a memory cell comprising a magnetic resistance device and lower and upper electrodes with the magnetic resistance device interposed therebetween to apply current to the magnetic resistance device. The magnetic resistance device includes: a buffer layer for controlling a crystalline axis for inducing perpendicular magnetic anisotropy (PMA) in the magnetic resistance device, the buffer layer being in contact with the lower electrode; a seed layer being in contact with the buffer layer and being oriented to a hexagonal close-packed lattice (HCP) (0001) crystal plane; and a perpendicularly magnetized pinned layer being in contact with the seed layer and having an L11 type ordered structure.
    Type: Application
    Filed: June 25, 2013
    Publication date: January 23, 2014
    Inventors: Yun-jae LEE, Woo-jin KIM, Joon-myoung LEE