Abstract: A method includes receiving a circuit design and a specification for the circuit design and determining a first hypothesized change to the circuit design. Making the first hypothesized change to the circuit design produces a first changed circuit design. The method also includes determining a first counterexample input that causes the first changed circuit design to produce an output that departs from the specification and determining a second hypothesized change to the circuit design based at least in part on the first hypothesized change. Making the second hypothesized change to the circuit design produces a second changed circuit design. The method further includes, in response to determining that the second changed circuit design has no counterexample input that causes the second changed circuit design to produce an output that departs from the specification, making the second hypothesized change to the circuit design.

Abstract: Disclosed is the present disclosure relates to a marine cable for offshore wind power having an improved water-tree property. More particularly, it relates to a marine cable for offshore wind power, which may effectively suppress formation of water trees caused by diffusion of moisture, having penetrated into cores of the cable, in insulating layers so as to improve dielectric strength and consequently secure a long lifespan.

Abstract: A pixel includes: a storage capacitor connected between a first power supply voltage and a gate node; a first transistor including a gate electrode connected to the gate node; a second transistor to transfer a data signal to a source of the first transistor in response to a scan signal; a third transistor to diode-connect the first transistor in response to the scan signal, and including first and second sub-transistors serially connected between the gate node and a drain of the first transistor; a fourth transistor to transfer an initialization voltage to the gate node in response to an initialization signal, and including third and fourth sub-transistors serially connected between the gate node and the initialization voltage; and an organic light emitting diode including a cathode connected to a second power supply voltage. At least one of the second and fourth sub-transistors includes a bottom electrode.

Abstract: The present invention relates to a chromatic confocal sensor based on a geometrical phase lens, and provides a chromatic confocal sensor that can confirm a height of a specimen and a location of a height measurement point through a configuration of a simple device.

Abstract: Embodiments are provided for providing enhanced fabrication and design of an integrated circuit in a computing system by a processor. One or more latches may be clustered by augmenting an integer linear program (“ILP”) operation with a facility-location allocation (FLA) operation, wherein the clustering of the one or more latches is timing-aware. The one or more latches may be placed and assigned in the integrated chip based on clustering one or more latches.

Abstract: Embodiments are provided for providing enhanced protection of an integrated circuit in a computing system by a processor. A logic locking FSM component or a logic locking with RTL gating may be applied to a current design logic to enable and protect operations of an integrated circuit, where the current design logic remains unchanged. The operation of the integrated circuit may be activated based upon providing to the integrated circuit a correct key from the logic locking FSM component or the logic locking with RTL gating.

Abstract: Embodiments are provided for enhanced initial global placement in a circuit design in a computing system by a processor. A wire length minimization may be determined based on maximum population density constraints as a single player game theory for global placement of an integrated circuit.

Abstract: Embodiments are provided for providing enhanced routing in a computing system by a processor. One or more of a plurality of short nets in a cell of an integrated circuit may be aligned for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold.

Abstract: Provided is a power cable, and particularly, to an ultra-high-voltage power cable of 45 kV to 600 kV. Specifically, the present invention relates to a power cable which is eco-friendly and includes an insulating layer formed of an insulating material having not only high heat resistance and mechanical strength but also high flexibility, bendability, impact resistance, cold resistance, installability, workability, etc., which are in trade-off with heat resistance and mechanical strength, and of which the lifespan, flexibility and installability can be additionally improved through precise control of a thickness of the insulating layer according to characteristics of the insulating material, thereby enhancing workability.

Abstract: Provided is a power cable including an insulating layer formed of an insulating material that is environmentally friendly and has not only high heat resistance and mechanical strength but also excellent flexibility, bendability, impact resistance, thermal stability, cold resistance, installability, workability, etc., which are trade-off with the physical properties.

Abstract: Design rule violations (“DRVs”) may be predicted using a design rule check (“DRC”) density map during a physical synthesis operation prior to executing a routing operation.

Abstract: Embodiments are provided for providing power staple avoidance during routing in a computing system by a processor. One or more transistor gates may be shifted in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, where the circuit row is partitioned into segments based on one or more fixed objects.

Abstract: Techniques regarding parameter tuning for an EDA protocol are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a tuning component that tunes an electronic design automation protocol via a cooperative co-evolutionary optimization framework that shares parameter knowledge across multiple stages of the electronic design automation protocol.

Abstract: Provided is a power cable including an insulating layer formed of an insulating material that is environmentally friendly and has not only high heat resistance and mechanical strength but also excellent flexibility, bendability, impact resistance, thermal stability, cold resistance, installability, workability, etc., which are trade-off with the physical properties.

Abstract: A data classification apparatus and method for providing expanded information are proposed. The method may include collecting time-series sensor data from an Internet-of-Things (IoT) sensor provided in or installable in a machine, and generating first processed data in which the time-series sensor data is highlighted. The method may also include generating, based on the first processed data, second processed data for determining a state of the machine, and classifying the state of the machine, based on the second processed data. The state of the machine may include one or more of a first state in which the machine is active and the first processed data is included in a non-pattern section in which no pattern is visualized, and a second state in which the machine is active and the first processed data is included in a pattern section in which an arbitrary pattern is visualized.

Abstract: Mechanisms are provided for optimizing an integrated circuit device design to obfuscate emissions corresponding to internal logic states of the integrated circuit device design. A first integrated circuit (IC) device design data structure is received and parsed to identify at least one instance of an obfuscation indicator in the data of the IC device design data structure. At least one IC logic element is marked, in the IC device design, which is associated with the at least one instance of the obfuscation indicator. At least one emission obfuscation optimization is applied to the marked at least one IC logic element to obfuscate emissions from the marked at least one IC logic element and generate an emissions obfuscated IC device design data structure. The emissions obfuscated IC device design data structure is output for fabrication of an IC device in accordance with the emissions obfuscated IC device design data structure.

Abstract: A method verifies an authenticity, integrity, and provenance of outputs from steps in a process flow. One or more processor(s) validate one or more inputs to each step in a process flow by verifying at least one of a hash and a digital signature of each of the one or more inputs. The processor(s) then generate digital signatures that cover outputs of each step and the one or more inputs to each step, such that the digital signatures result in a chain of digital signatures that are used to verify an authenticity, an integrity and a provenance of outputs of the one or more steps in the process flow.

Abstract: Provided is an insulator that is environmentally friendly and has high heat resistance and mechanical strength and excellent flexibility, bendability, impact resistance, cold resistance, installability, workability, etc., which are in a trade-off relationship with the physical properties; and a power cable having the insulator.

Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.