Abstract: A cooling apparatus of a plasma display panel and a method for stabilizing the PDP to minimize the residual image on the display are disclosed. In particular, the present invention minimizes the residual image that is generated due to the degeneration of phosphors caused by a high voltage and a high temperature.

Abstract: A polypropylene resin, useful for the production of biaxially oriented polypropylene (BOPP) film, is provided. The polymer of the present invention is a blend of high crystalline polypropylene homopolymer and a high ethylene ethylene/propylene random copolymer (RCP). The present invention also provides a method of preparing the novel resin as well as a novel BOPP film comprising the resin.

Abstract: A polypropylene resin, useful for the production of biaxially oriented polypropylene (BOPP) film, is provided. The polymer of the present invention is a blend of high crystalline polypropylene homopolymer and a high ethylene ethylene/propylene random copolymer (RCP). The present invention also provides a method of preparing the novel resin as well as a novel BOPP film comprising the resin.

Abstract: A polypropylene resin, useful for the production of biaxially oriented polypropylene (BOPP) film, is provided. The polymer of the present invention is a blend of high crystalline polypropylene homopolymer and a high ethylene ethylene/propylene random copolymer (RCP). The present invention also provides a method of preparing the novel resin as well as a novel BOPP film comprising the resin.

Abstract: A polypropylene resin, useful for the production of biaxially oriented polypropylene (BOPP) film, is provided. The polymer of the present invention is a blend of high crystalline polypropylene homopolymer and a high ethylene ethylene/propylene random copolymer (RCP). The present invention also provides a method of preparing the novel resin as well as a novel BOPP film comprising the resin.

Abstract: A gate conductor including a gate line, a gate pad and a gate electrode is formed on a substrate. A gate insulating layer, a semiconductor layer, a doped amorphous silicon layer and a conductive layer are deposited in sequence, and then a photoresist film pattern is formed thereon. The photoresist film pattern includes a first portion positioned between the to be formed source electrode and drain electrode, a second portion thicker than the first portion, and the third portion with no photoresist. A data conductor including a data line, a data pad, a source electrode, a drain electrode and a conductor pattern for a storage capacitor, an ohmic contact layer pattern and a semiconductor pattern are formed by etching the conductive layer, the doped amorphous silicon layer and the semiconductor layer using the photoresist film pattern. A plurality of color filters of red, green and blue having apertures exposing part of the drain electrode are formed thereon.

Abstract: A cooling apparatus of a plasma display panel and a method for stabilizing the PDP to minimize the residual image on the display are disclosed. In particular, the present invention minimizes the residual image that is generated due to the degeneration of phosphors caused by a high voltage and a high temperature.

Abstract: Thin film transistors are formed on a lower substrate, and red, green, blue and transparent color filters are formed thereon. An organic insulating layer is formed on the color filters, and pixel electrodes are formed thereon. A black matrix and a common electrode are formed on an upper substrate facing the lower substrate.

Abstract: Thin film transistors are formed on a lower substrate, and red, green, blue and transparent color filters are formed thereon. An organic insulating layer is formed on the color filters, and pixel electrodes are formed thereon. A black matrix and a common electrode are formed on an upper substrate facing the lower substrate.

Abstract: A cooling apparatus of a plasma display panel and a method for stabilizing the PDP to minimize the residual image on the display are disclosed. In particular, the present invention minimizes the residual image that is generated due to the degeneration of phosphors caused by a high voltage and a high temperature.

Abstract: A thin film panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line that intersects the first signal line and includes first and second portions being substantially rectilinear and disposed on different straight lines and a connection connected to the first and the second portions; and first and second pixel electrodes disposed adjacent to the second signal line and overlapping the first and the second portions of the second signal line, respectively.

Abstract: A method of driving a plasma display apparatus is disclosed. In the method, a first reset pulse including a rising pulse and a falling pulse is applied to a scan electrode during a reset period of a first subfield of a plurality of subfields. A second reset pulse including a rising pulse and a falling pulse is applied to the scan electrode during a reset period of a turn-on subfield next to a turn-off subfield in the remaining subfields except the first subfield. A third reset pulse including a falling pulse is applied to the scan electrode during a reset period of another subfield except the subfields during which the first reset pulse and the second reset pulse are applied.

Abstract: A thin film transistor array panel is provided, which includes: a gate line; first and second data lines insulated from the gate line; a thin film transistor connected to the gate line and the first data line; a pixel electrode disposed between the first data line and the second data line, spaced apart from the first and the second data lines, and coupled to the thin film transistor; and first and second projections connected to the pixel electrode and overlapping the first and the second data lines, respectively.

Abstract: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a—Si layer, an extrinsic a—Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a—Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a—Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.

Abstract: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.

Abstract: The present invention discloses a plasma display panel and method for manufacturing the same wherein the quality of an image can be improved by preventing an erroneous discharge. A plasma display panel having a number of discharge cells according to an embodiment of the present invention includes barrier ribs by which a discharge space is defined between an upper substrate and a lower substrate; and an oxide film of a low dielectric constant formed on each of the barrier ribs. A method for manufacturing a plasma display panel according to an embodiment of the present invention includes the steps of: forming barrier ribs on a lower substrate so that a discharge space is defined by the barrier ribs between an upper substrate and a lower substrate; and forming an oxide film of a low dielectric constant on each of the barrier ribs.

Abstract: A thin film panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line that intersects the first signal line and includes first and second portions being substantially rectilinear and disposed on different straight lines and a connection connected to the first and the second portions; and first and second pixel electrodes disposed adjacent to the second signal line and overlapping the first and the second portions of the second signal line, respectively.

Abstract: A thin film panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line that intersects the first signal line and includes first and second portions being substantially rectilinear and disposed on different straight lines and a connection connected to the first and the second portions; and first and second pixel electrodes disposed adjacent to the second signal line and overlapping the first and the second portions of the second signal line, respectively.

Abstract: A gate conductor including a gate line, a gate pad and a gate electrode is formed on a substrate. A gate insulating layer, a semiconductor layer, a doped amorphous silicon layer and a conductive layer are deposited in sequence, and then a photoresist film pattern is formed thereon. The photoresist film pattern includes a first portion positioned between the to be formed source electrode and drain electrode, a second portion thicker than the first portion, and the third portion with no photoresist. A data conductor including a data line, a data pad, a source electrode, a drain electrode and a conductor pattern for a storage capacitor, an ohmic contact layer pattern and a semiconductor pattern are formed by etching the conductive layer, the doped amorphous silicon layer and the semiconductor layer using the photoresist film pattern. A plurality of color filters of red, green and blue having apertures exposing part of the drain electrode are formed thereon.

Abstract: A liquid crystal display is provided, which includes a gate line formed on a first insulating substrate, a data line intersecting the gate line and insulated from the gate line, a pixel electrode provided in a pixel area defined by the intersection of the gate line and the data line, a second insulating substrate facing the first insulating substrate, a common electrode formed on the second insulating substrate, a liquid crystal layer interposed between the pixel electrode and the common electrode, a first cutout in the pixel electrode, and a second cutout provided in the common electrode and partitioning the pixel area into a plurality of domains along with the first cutout. The plurality of domains in the pixel area are classified into at least two types based on the presence of an organic insulating layer.