Abstract: Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip.

Abstract: Disclosed are PQFN semiconductor die packages for high-voltage, high-power applications, systems using the packages, and methods of making the packages. An exemplary package comprises a leadframe, a semiconductor die disposed on the leadframe, and a heat sink member disposed on the semiconductor die and the leadframe and integrated into the molding material of the package. The heat sink member has an electrically insulating substrate with a high breakdown voltage, and one or more conductive layers disposed on a first surface of the substrate that electrically interconnect the semiconductor to one or more leads of the leadframe.

Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.

Abstract: Disclosed are PQFN semiconductor die packages for high-voltage, high-power applications, systems using the packages, and methods of making the packages. An exemplary package comprises a leadframe, a semiconductor die disposed on the leadframe, and a heat sink member disposed on the semiconductor die and the leadframe and integrated into the molding material of the package. The heat sink member has an electrically insulating substrate with a high breakdown voltage, and one or more conductive layers disposed on a first surface of the substrate that electrically interconnect the semiconductor to one or more leads of the leadframe.

Abstract: Provided are semiconductor packages and methods of fabricating the same. An exemplary semiconductor package includes a die pad including a dimple filled with an insulating material in an upper surface or a lower surface thereof. A semiconductor chip is mounted on the upper surface of the first die pad. A package body encapsulates the first die pad and the first semiconductor chip and includes a pinhole. A bottom surface of the pinhole terminates at the insulating material.

Abstract: Provided are a power module including a power package and a control package that are provided separately and can be highly integrated, and method of fabricating the power module. The power module includes: a molded power package including at least one power device on a first lead frame; and a molded control package vertically stacked on the power package, and including at least one control device on a second lead frame. A first part of the first lead frame and a first part of the second lead frame are coupled to each other so that the power package and the control package can be electrically coupled to each other.

Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.

Abstract: Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module.

Abstract: Provided is a semiconductor device package including a substrate formed of a silicon (Si)-based material. The semiconductor device package includes a first substrate which comprises first and second principal planes which are opposite each other, and a substrate body layer disposed between the first and second principal planes, the substrate body layer being formed of a silicon (Si)-based material; and at least one first semiconductor device which is mounted on the first principal plane.

Abstract: Provided are power device substrates that comprise thermally conductive plastic materials, and power device packages including the same. An exemplary power device package includes a power device substrate that comprises a thermally conductive plastic material, and has a first principal plane that provides an electrically insulating surface and a second principal plane of which at least a portion is exposed outside a molding member. The exemplary power device package further includes one or more power devices disposed on the first principal plane of the power device substrate, and a plurality of conductive members that are electrically connected to the power device(s) in order to electrically connect the power device(s) to an external circuit.

Abstract: Provided is a semiconductor package having a power device and methods of fabricating the same. The semiconductor package includes a lead frame, a polymer layer component on the lead frame, a metal layer component on the polymer layer component, and a semiconductor chip on the metal layer component. The polymer layer component may include a material formed by adding alumina Al2O3 an aluminum nitride (AlN), or a boron nitride BN to an epoxy resin. The polymer layer component may have high thermal conductivity and good electric insulating characteristics.

Abstract: Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip.

Abstract: Provided are a power module including a power package and a control package that are provided separately and can be highly integrated, and method of fabricating the power module. The power module includes: a molded power package including at least one power device on a first lead frame; and a molded control package vertically stacked on the power package, and including at least one control device on a second lead frame. A first part of the first lead frame and a first part of the second lead frame are coupled to each other so that the power package and the control package can be electrically coupled to each other.

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first die-pad on which a semiconductor chip is mounted on a bottom surface of the first die-pad, a support plate disposed adjacent to a lateral surface of the first die-pad, a support prop protruding from the support plate, and supporting the first die-pad, and a package body that encapsulates the first die-pad, the semiconductor chip, and the support plate.

Abstract: Provided are semiconductor packages and methods of fabricating the same. An exemplary semiconductor package includes a die pad including a dimple filled with an insulating material in an upper surface or a lower surface thereof. A semiconductor chip is mounted on the upper surface of the first die pad. A package body encapsulates the first die pad and the first semiconductor chip and includes a pinhole. A bottom surface of the pinhole terminates at the insulating material.

Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.

Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.

Abstract: A semiconductor package has a structure in which a leadframe pad to which a semiconductor die is attached and inner leads electrically connected to the leadframe pad are covered by a molded housing, and outer leads extending from the inner leads protrude from a side surface of the molded housing to the outside. The outer leads include a first outer lead disposed in a central portion of the molded housing, second and third outer leads respectively disposed in a right and left of the first outer lead. The second and third outer leads each have bent portions in portions where they are adjacent to the side surface of the molded housing, the bent portions protruding to increase a space between the first outer lead and the bent portions in the molded housing. At least one of the bent portions of the second and third outer leads is covered by an extended portion of the molded housing.

Abstract: A semiconductor package has a structure in which a leadframe pad to which a semiconductor die is attached and inner leads electrically connected to the leadframe pad are covered by a molded housing, and outer leads extending from the inner leads protrude from a side surface of the molded housing to the outside. The outer leads include a first outer lead disposed in a central portion of the molded housing, second and third outer leads respectively disposed in a right and left of the first outer lead. The second and third outer leads each have bent portions in portions where they are adjacent to the side surface of the molded housing, the bent portions protruding to increase a space between the first outer lead and the bent portions in the molded housing. At least one of the bent portions of the second and third outer leads is covered by an extended portion of the molded housing.

Abstract: A semiconductor package has a structure in which a leadframe pad to which a semiconductor die is attached and inner leads electrically connected to the leadframe pad are covered by a molded housing, and outer leads extending from the inner leads protrude from a side surface of the molded housing to the outside. The outer leads include a first outer lead disposed in a central portion of the molded housing, second and third outer leads respectively disposed in a right and left of the first outer lead. The second and third outer leads each have bent portions in portions where they are adjacent to the side surface of the molded housing, the bent portions protruding to increase a space between the first outer lead and the bent portions in the molded housing. At least one of the bent portions of the second and third outer leads is covered by an extended portion of the molded housing.