Abstract: The present disclosure relates to a computing system. The computing system may include a memory system including a plurality of memory devices configured to store raw data and a near data processor (NDP) configured to receive the raw data by a first bandwidth from the plurality of memory devices and generate intermediate data by performing a first operation on the raw data, and a host device coupled to the memory system by a second bandwidth and determining a resource to perform a second operation on the intermediate data based on a bandwidth ratio and a data size ratio.

Abstract: The present disclosure relates to a computing system. The computing system may include a memory system including a plurality of memory devices configured to store raw data and a near data processor (NDP) configured to receive the raw data by a first bandwidth from the plurality of memory devices and generate intermediate data by performing a first operation on the raw data, and a host device coupled to the memory system by a second bandwidth and determining a resource to perform a second operation on the intermediate data based on a bandwidth ratio and a data size ratio.

Abstract: In an embodiment of the disclosed technology, a storage device includes a circuit board, a memory disposed on the circuit board and including a plurality of memory cells configured to store data, and an internal processor coupled to be in communication with the memory and configured to perform an operation on the data stored in the memory upon receipt of a command from an external device, wherein the command is extracted based on an operational intensity of the operation to be performed in response to the command, in a process in which a compiler generates an instruction according to a program executed by an external processor that is disposed outside the memory and separate from the internal processor.

Abstract: An interface device may communicate between a first device and a second device. The interface device may comprise a first element configured to receive a first packet from the first device based on a first protocol and transmit the first packet to the second device, wherein the first packet includes a command and a command address representing a storage position of the command, and a second element configured to receive a second packet from the first device based on a second protocol different from the first protocol and transmit the second packet to the second device, wherein the second packet includes the command address.

Abstract: A memory system for efficiently processing data in performing a job may include a plurality of memory devices configured to store data, a main data processor configured to access the plurality of memory devices, a sub data processor group including a plurality of sub data processors each configured to access the plurality of memory devices, respectively, a host interface configured to receive, from a host, a request for a job, and a job controller configured to perform the job by using one of the main data processor and the sub data processor group depending on whether accesses to the plurality of memory devices are related to each other for the job.

Abstract: A system for classifying data may include a memory, and a processor configured to determine a scan target including a data group selected from among data groups stored in the memory, based on a result of a comparison between first similarities of data groups stored in the memory and an externally received query, and a minimum value of second similarities of pieces of data included in a data group having a maximum value of the first similarities and the query, and to output, as result data responding to the query, scan data selected depending on a reference number of pieces of scan data from among pieces of scan data in the data group included in the scan target.

Abstract: The present disclosure relates to a computing system. The computing system may include a memory system including a plurality of memory devices configured to store raw data and a near data processor (NDP) configured to receive the raw data by a first bandwidth from the plurality of memory devices and generate intermediate data by performing a first operation on the raw data, and a host device coupled to the memory system by a second bandwidth and determining a resource to perform a second operation on the intermediate data based on a bandwidth ratio and a data size ratio.

Abstract: A computing system capable of reducing data movement during an embedding operation and efficiently processing the embedding operation includes a host and a memory system. The host divides a plurality of feature tables, each including a respective plurality of embedding vectors for a respective plurality of elements, into a first feature table group and a second feature table group; generates a first embedding table configured of the first feature table group; and sends a request for a generation operation of a second embedding table configured of the second feature table group to the memory system. The memory system generates the second embedding table according to the generation operation request provided by the host. The host divides the plurality of feature tables into the first feature table group and the second feature table group based on the number of elements included in each of the plurality of feature tables.

Abstract: A computing system capable of reducing data movement during an embedding operation and efficiently processing the embedding operation includes a host and a memory system. The host divides a plurality of feature tables, each including a respective plurality of embedding vectors for a respective plurality of elements, into a first feature table group and a second feature table group; generates a first embedding table configured of the first feature table group; and sends a request for a generation operation of a second embedding table configured of the second feature table group to the memory system. The memory system generates the second embedding table according to the generation operation request provided by the host. The host divides the plurality of feature tables into the first feature table group and the second feature table group based on the number of elements included in each of the plurality of feature tables.

Abstract: Methods, systems, and devices for alleviating a bandwidth bottleneck during an embedding operation are described. An example storage device, based on the disclosed technology, includes a memory device configured to store matrix data, a memory controller, coupled to the memory device, configured to receive, from a host, non-zero data and the index of the non-zero data, and generate vector data based on the non-zero data and the index, and an operating component, coupled to the memory device and the memory controller, configured to perform a multiplication operation between the matrix data and the vector data.

Abstract: An electronic device including a semiconductor memory is provided to include a mat region comprising a plurality of memory cells, each including a second transistor; a first switching region located at a side of the mat region and including first transistors; and a second switching region located at the other side of the mat region and including third transistors, wherein the second transistors comprise: a plurality of second active regions; and a plurality of second gate structures extending in the first direction to cross the second active regions, wherein each second active regions is divided into a first side portion, a middle portion and a second side portion that are arranged alternately and repeatedly in the first direction, wherein the first transistors and the third transistors include their active regions and gate structures which are arranged in the same manner as those of the second transistors.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a first portion of a variable resistance element, the first portion having an island shape and including at least a free layer which has a variable magnetization direction; a second portion of the variable resistance element, the second portion having a line shape which extends in a direction over the first portion and including at least a pinned layer which has a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a first portion of a variable resistance element, the first portion having an island shape and including at least a free layer which has a variable magnetization direction; a second portion of the variable resistance element, the second portion having a line shape which extends in a direction over the first portion and including at least a pinned layer which has a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer.

Abstract: An electronic device including a semiconductor memory is provided to include a mat region comprising a plurality of memory cells, each including a second transistor; a first switching region located at a side of the mat region and including first transistors; and a second switching region located at the other side of the mat region and including third transistors, wherein the second transistors comprise: a plurality of second active regions; and a plurality of second gate structures extending in the first direction to cross the second active regions, wherein each second active regions is divided into a first side portion, a middle portion and a second side portion that are arranged alternately and repeatedly in the first direction, wherein the first transistors and the third transistors include their active regions and gate structures which are arranged in the same manner as those of the second transistors.

Abstract: An electronic device includes a semiconductor device that includes: a substrate including a switching element having a buried gate electrode; a buried decoupling capacitor having a line width same as a line width of the buried gate electrode; and a variable resistance element, electrically coupled to the switching element, formed over the substrate.

Abstract: Provided is an electronic device including a semiconductor memory which includes a first region in which a first variable resistance element for storing data is disposed; and a second region in which a reference resistance element for sensing data stored in the first variable resistance element is disposed, and wherein the reference resistance element comprising: a plurality of second variable resistance elements formed of the same material at the same level as the first variable resistance element; a plurality of contacts coupled to each of the second variable resistance elements; and a first pad coupled to part of the contacts which are coupled to one of two adjacent second variable resistance elements and part of the contacts which are coupled to the other of the two adjacent second variable resistance elements for coupling the two adjacent second variable resistance elements with each other.

Abstract: An electronic device includes a semiconductor device that includes: a substrate including a switching element having a buried gate electrode; a buried decoupling capacitor having a line width same as a line width of the buried gate electrode; and a variable resistance element, electrically coupled to the switching element, formed over the substrate.

Abstract: A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source.

Abstract: A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source.

Abstract: An electronic device includes a semiconductor device that includes: a substrate including a switching element having a buried gate electrode; a buried decoupling capacitor having a line width same as a line width of the buried gate electrode; and a variable resistance element, electrically coupled to the switching element, formed over the substrate.