Abstract: A method for replicating a holographic optical element and a holographic optical element replicated thereby are provided. The holographic optical element is larger than a master. The master has a holographic grating pattern generated on the master by interference of the reflected, diffracted or transmitted beam generated by irradiating the master having a specific diffraction grating pattern formed thereon with a laser beam.

Abstract: A non-volatile memory device includes a memory cell array to which an arithmetic internal data is written; and an arithmetic circuitry configured to receive an arithmetic input data and the arithmetic internal data for an arithmetic operation of a neural network with the arithmetic internal data and the arithmetic input data in response to an arithmetic command, perform the arithmetic operation using the arithmetic internal data and the arithmetic input data to generate an arithmetic result data, and output the arithmetic result data of the arithmetic operation of the neural network.

Abstract: A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.

Abstract: A non-volatile memory device includes a memory cell array to which an arithmetic internal data is written; and an arithmetic circuitry configured to receive an arithmetic input data and the arithmetic internal data for an arithmetic operation of a neural network with the arithmetic internal data and the arithmetic input data in response to an arithmetic command, perform the arithmetic operation using the arithmetic internal data and the arithmetic input data to generate an arithmetic result data, and output the arithmetic result data of the arithmetic operation of the neural network.

Abstract: A memory device can include: a memory cell array including a memory cell and a word line that is connected to the memory cell; a clock generator configured to generate a first pumping clock signal from a system clock signal; a charge pump configured to provide a pumping voltage signal using a power supply voltage and the first pumping clock signal; a compensation circuit configured to compensate for variations in a first reference clock signal in accordance with variations in the power supply voltage, and provide a compensated first reference clock signal; and a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing the first pumping clock signal and the compensated first reference clock signal while the pumping voltage signal is provided to the word line.

Abstract: A memory device can include: a memory cell array including a memory cell and a word line that is connected to the memory cell; a clock generator configured to generate a first pumping clock signal from a system clock signal; a charge pump configured to provide a pumping voltage signal using a power supply voltage and the first pumping clock signal; a compensation circuit configured to compensate for variations in a first reference clock signal in accordance with variations in the power supply voltage, and provide a compensated first reference clock signal; and a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing the first pumping clock signal and the compensated first reference clock signal while the pumping voltage signal is provided to the word line.

Abstract: A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.

Abstract: In a method of operating a storage device including at least one nonvolatile memory device and a memory controller configured to control the at least one nonvolatile memory device, a boundary page of a first memory block among a plurality of memory blocks included in the at least one nonvolatile memory device is searched for, at least one clean page, in which data is not written, of the first memory block is searched for, a dummy program operation is performed on a portion of the boundary page and the at least one clean page, and an erase operation is performed on the first memory block.

Abstract: In a method of operating a storage device including at least one nonvolatile memory device and a memory controller configured to control the at least one nonvolatile memory device, a boundary page of a first memory block among a plurality of memory blocks included in the at least one nonvolatile memory device is searched for, at least one clean page, in which data is not written, of the first memory block is searched for, a dummy program operation is performed on a portion of the boundary page and the at least one clean page, and an erase operation is performed on the first memory block.

Abstract: A method of programming a memory device includes programming a low bit to a memory cell included in a word line and a bit line based on a first verification condition, the low bit belonging to a group of bits including a high bit. The first verification condition is based on at least one of a first bit line current, a first develop time for verifying the programming of the low bit, and a first word line voltage. The method includes programming the high bit to the memory cell based on a second verification condition. The second verification condition is based on at least one of a second bit line current, a second develop time for verifying the programming of the high bit, and a second word line voltage.

Abstract: A method of programming a memory device includes programming a low bit to a memory cell included in a word line and a bit line based on a first verification condition, the low bit belonging to a group of bits including a high bit. The first verification condition is based on at least one of a first bit line current, a first develop time for verifying the programming of the low bit, and a first word line voltage. The method includes programming the high bit to the memory cell based on a second verification condition. The second verification condition is based on at least one of a second bit line current, a second develop time for verifying the programming of the high bit, and a second word line voltage.