Abstract: A display device includes a supporting substrate including a polymeric material, base substrate disposed on an upper surface of the supporting substrate, a pixel array disposed in a display area of the base substrate, a transfer wiring disposed in a bending area of the base substrate and electrically connected to the pixel array, and an organic filling portion disposed under the transfer wiring in the bending area. The base substrate includes an organic film including a polymeric material, and an inorganic barrier film overlapping the organic film and extending outwardly from an edge of the organic film. The organic filling portion contacts the organic film of the base substrate.

Abstract: A display device includes: a first substrate; a plurality of metal layers on the first substrate and separated from each other; a buffer layer on the metal layer; a semiconductor layer on the buffer layer; a gate conductive layer on the semiconductor layer; a data conductive layer connected to the semiconductor layer; and a light-emitting element connected to the data conductive layer, wherein the metal layer includes a first portion partially overlapping the semiconductor layer in a third direction perpendicular to the surface of the first substrate, a second portion where the metal layer completely overlaps the semiconductor layer in the third direction, and a third portion where the metal layer does not overlap the semiconductor layer in the third direction.

Abstract: A semiconductor device includes a substrate including an active region having an isolated shape and a field region. A gate insulation layer is provided on an upper surface of the active region of the substrate. A gate electrode is provided on the gate insulation layer and spaced apart from the boundary of the active region to cover the middle portion of the active region. An impurity region is provided under a surface of the active region that is exposed by the gate electrode.

Abstract: A semiconductor device includes a substrate including an active region having an isolated shape and a field region. A gate insulation layer is provided on an upper surface of the active region of the substrate. A gate electrode is provided on the gate insulation layer and spaced apart from the boundary of the active region to cover the middle portion of the active region. An impurity region is provided under a surface of the active region that is exposed by the gate electrode.

Abstract: A method for coating a substrate with a plate type nanomaterial is provided. The method involves preparing a dispersed solution containing the plate type nanomaterial and a surface active agent, dipping the substrate into the dispersed solution, and drying the substrate after withdrawing the substrate from the dispersed solution. Also provided herein are a dipping solution used for coating the substrate, and a method of preparing a dipping solution for coating a substrate with a plate type nanomaterial.

Abstract: According to an example embodiment a method of plating resin using a graphene thin layer includes forming a graphene thin layer on a resin substrate and electroplating the resin substrate having the graphene thin layer fog on the resin substrate.

Abstract: A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may be formed under a portion of the schottky junction.

Abstract: A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may be formed under a portion of the schottky junction.

Abstract: Some embodiments of the present invention provide high voltage transistors including a semiconductor substrate and a device isolation film defining an active region in the semiconductor substrate. A gate electrode extends along a central portion of the active region while maintaining a predetermined width on the semiconductor substrate. A second well is formed on both sides of the gate electrode in the semiconductor substrate, and partially extends to a bottom surface of the device isolation film. The active region in the semiconductor substrate comprises a first active region disposed under the gate electrode, and separating the device isolation film and a second active region defined by the first active region and the device isolation film. Methods of manufacturing high voltage transistors are also provided.

Abstract: Diamine compound containing specific triazine group, polyamic acid obtained by reacting the diamine compound and tetracarboxylic dianhydride, and liquid crystal alignment film obtained by coating and imidizing the polyamic acid. The liquid crystal alignment film has good heat-resistance, high transparency in visible light region and improved voltage holding ratio. Also, pretilt angle is easily controlled over broad range.

Abstract: A method of forming a metal silicide layer includes sequentially forming a metal layer and a first capping layer on a substrate, performing a first heat treatment on the substrate to cause the substrate to react to the metal layer, removing the first, capping layer and an unreacted metal layer, forming a second capping layer on the substrate, and performing a second heat treatment on the substrate to form a metal silicide layer on the substrate.

Abstract: Some embodiments of the present invention provide high voltage transistors including a semiconductor substrate and a device isolation film defining an active region in the semiconductor substrate. A gate electrode extends along a central portion of the active region while maintaining a predetermined width on the semiconductor substrate. A second well is formed on both sides of the gate electrode in the semiconductor substrate, and partially extends to a bottom surface of the device isolation film. The active region in the semiconductor substrate comprises a first active region disposed under the gate electrode, and separating the device isolation film and a second active region defined by the first active region and the device isolation film. Methods of manufacturing high voltage transistors are also provided.

Abstract: A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may, be formed under a portion of the schottky junction.