Patents by Inventor Joon Suk Oh

Joon Suk Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8907391
    Abstract: A semiconductor device includes a substrate including an active region having an isolated shape and a field region. A gate insulation layer is provided on an upper surface of the active region of the substrate. A gate electrode is provided on the gate insulation layer and spaced apart from the boundary of the active region to cover the middle portion of the active region. An impurity region is provided under a surface of the active region that is exposed by the gate electrode.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: December 9, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Jung-Soo Nam, Joon-Suk Oh, Hye-Young Park
  • Publication number: 20130161711
    Abstract: A semiconductor device includes a substrate including an active region having an isolated shape and a field region. A gate insulation layer is provided on an upper surface of the active region of the substrate. A gate electrode is provided on the gate insulation layer and spaced apart from the boundary of the active region to cover the middle portion of the active region. An impurity region is provided under a surface of the active region that is exposed by the gate electrode.
    Type: Application
    Filed: September 13, 2012
    Publication date: June 27, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Soo NAM, Joon-Suk Oh, Hye-Young Park
  • Publication number: 20120237692
    Abstract: A method for coating a substrate with a plate type nanomaterial is provided. The method involves preparing a dispersed solution containing the plate type nanomaterial and a surface active agent, dipping the substrate into the dispersed solution, and drying the substrate after withdrawing the substrate from the dispersed solution. Also provided herein are a dipping solution used for coating the substrate, and a method of preparing a dipping solution for coating a substrate with a plate type nanomaterial.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 20, 2012
    Inventors: Jae Do NAM, Joon Suk Oh, Tae Seon Hwang
  • Publication number: 20110284388
    Abstract: According to an example embodiment a method of plating resin using a graphene thin layer includes forming a graphene thin layer on a resin substrate and electroplating the resin substrate having the graphene thin layer fog on the resin substrate.
    Type: Application
    Filed: April 1, 2011
    Publication date: November 24, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ah Hyun Bae, Sang Ik Son, Jae Do Nam, Jun Ho Lee, Tae Seon Hwang, Joon Suk Oh
  • Patent number: 8018021
    Abstract: A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may be formed under a portion of the schottky junction.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: September 13, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Shik Kim, Oh-Kyum Kwon, Myung-Hee Kim, Yong-Chan Kim, Hye-Young Park, Joon-Suk Oh
  • Publication number: 20100200945
    Abstract: A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may be formed under a portion of the schottky junction.
    Type: Application
    Filed: April 19, 2010
    Publication date: August 12, 2010
    Inventors: Dae-Shik Kim, Oh-Kyum Kwon, Myung-Hee Kim, Yong-Chan Kim, Hye-Young Park, Joon-Suk Oh
  • Patent number: 7705409
    Abstract: Some embodiments of the present invention provide high voltage transistors including a semiconductor substrate and a device isolation film defining an active region in the semiconductor substrate. A gate electrode extends along a central portion of the active region while maintaining a predetermined width on the semiconductor substrate. A second well is formed on both sides of the gate electrode in the semiconductor substrate, and partially extends to a bottom surface of the device isolation film. The active region in the semiconductor substrate comprises a first active region disposed under the gate electrode, and separating the device isolation film and a second active region defined by the first active region and the device isolation film. Methods of manufacturing high voltage transistors are also provided.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: April 27, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Oh-kyum Kwon, Yong-chan Kim, Joon-suk Oh, Myung-hee Kim, Hye-young Park
  • Patent number: 7635746
    Abstract: Diamine compound containing specific triazine group, polyamic acid obtained by reacting the diamine compound and tetracarboxylic dianhydride, and liquid crystal alignment film obtained by coating and imidizing the polyamic acid. The liquid crystal alignment film has good heat-resistance, high transparency in visible light region and improved voltage holding ratio. Also, pretilt angle is easily controlled over broad range.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: December 22, 2009
    Assignee: Cheil Industries Inc.
    Inventors: Jae Min Oh, Bum Jin Lee, Moo Young Lee, O Bum Kwon, Joon Suk Oh, Dong Won Park, Chul Hee Kim
  • Publication number: 20080293205
    Abstract: A method of forming a metal silicide layer includes sequentially forming a metal layer and a first capping layer on a substrate, performing a first heat treatment on the substrate to cause the substrate to react to the metal layer, removing the first, capping layer and an unreacted metal layer, forming a second capping layer on the substrate, and performing a second heat treatment on the substrate to form a metal silicide layer on the substrate.
    Type: Application
    Filed: May 22, 2008
    Publication date: November 27, 2008
    Inventors: Oh-Kyum KWON, Bum-Seok KIM, Geun-Sook PARK, Joon-Suk OH, Hye-Young PARK, Min-Jun CHOI
  • Publication number: 20080185664
    Abstract: Some embodiments of the present invention provide high voltage transistors including a semiconductor substrate and a device isolation film defining an active region in the semiconductor substrate. A gate electrode extends along a central portion of the active region while maintaining a predetermined width on the semiconductor substrate. A second well is formed on both sides of the gate electrode in the semiconductor substrate, and partially extends to a bottom surface of the device isolation film. The active region in the semiconductor substrate comprises a first active region disposed under the gate electrode, and separating the device isolation film and a second active region defined by the first active region and the device isolation film. Methods of manufacturing high voltage transistors are also provided.
    Type: Application
    Filed: January 15, 2008
    Publication date: August 7, 2008
    Inventors: Oh-kyum Kwon, Yong-chan Kim, Joon-suk Oh, Myung-hee Kim, Hye-young Park
  • Publication number: 20080006899
    Abstract: A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may, be formed under a portion of the schottky junction.
    Type: Application
    Filed: May 4, 2007
    Publication date: January 10, 2008
    Inventors: Dae-Shik Kim, Oh-Kyum Kwon, Myung-Hee Kim, Yong-Chan Kim, Hye-Young Park, Joon-Suk Oh