Abstract: An electrostatic discharge (ESD) protection circuit includes an ESD detector connected between a pad and a first power source and configured to generate a detection signal when ESD is detected at the pad, a switch transistor including a gate controlled by the detection signal and a source and a drain connected between the pad and the memory, and a leakage current prevention circuit including a first transistor including a first gate connected to a second power source and a source and a drain connected between the pad and a first node, and a second transistor including a second gate connected to the pad and a source and a drain connected between the first node and the second power source. The first node is connected to or in electrical communication with a bulk node of the switch transistor.

Abstract: An input/output circuit for a memory and a method of controlling the same are disclosed. The input/output circuit and the method of controlling the same are configured to prevent a memory element from being falsely or incorrectly programmed due to an ESD pulse. More particularly, the input/output circuit and the method of controlling the same include an ESD detection unit configured to detect a programming voltage or an ESD pulse on a pad terminal, a control logic unit configured to transmit a first voltage or a second voltage according to the programming voltage and the ESD pulse, and a switch unit configured to perform a turn-on or turn-off operation according to the first voltage or the second voltage.

Abstract: An ESD protection circuit for an input/output buffer in which when an ESD pulse or event occurs, an ESD surge on a pad is discharged to a diode and a transistor channel, thereby enhancing the efficiency of the ESD protection circuit. The ESD protection circuit includes a floating N-well bias circuit connected to a pad at an output of driver circuit and outputting a bias voltage based on or in response to a supply voltage; a switch circuit connected to a logic circuit and the driver circuit, and configured to connect and disconnect the logic circuit and the driver circuit based on or in response to the supply voltage; and a pull-down circuit connected to the driver circuit, configured to output a voltage to the driver circuit based on or in response to the supply voltage.

Abstract: An electrostatic discharge (ESD) protection circuit includes an ESD detector connected between a pad and a first power source and configured to generate a detection signal when ESD is detected at the pad, a switch transistor including a gate controlled by the detection signal and a source and a drain connected between the pad and the memory, and a leakage current prevention circuit including a first transistor including a first gate connected to a second power source and a source and a drain connected between the pad and a first node, and a second transistor including a second gate connected to the pad and a source and a drain connected between the first node and the second power source. The first node is connected to or in electrical communication with a bulk node of the switch transistor.

Abstract: A voltage on-off detector includes an inverter between a first voltage source and a third voltage source providing a third voltage and having an input terminal that receives a second voltage, a first transistor having a gate that receives the second voltage, and a first source and a first drain between the third voltage source and a first node, a second transistor having a second gate that receives the third voltage, and a second source and a second drain between a second voltage source providing the second voltage and the first node, and an amplifier configured to output a first voltage from the first voltage source or a voltage on the first node based on or in response to an output of the inverter.

Abstract: An ESD protection circuit for an input/output buffer in which when an ESD pulse or event occurs, an ESD surge on a pad is discharged to a diode and a transistor channel, thereby enhancing the efficiency of the ESD protection circuit. The ESD protection circuit includes a floating N-well bias circuit connected to a pad at an output of driver circuit and outputting a bias voltage based on or in response to a supply voltage; a switch circuit connected to a logic circuit and the driver circuit, and configured to connect and disconnect the logic circuit and the driver circuit based on or in response to the supply voltage; and a pull-down circuit connected to the driver circuit, configured to output a voltage to the driver circuit based on or in response to the supply voltage.

Abstract: A voltage on-off detector includes an inverter between a first voltage source and a first node and having an input terminal that receives a third voltage, a first transistor having a first gate, and a first source and a first drain between the first node and a second voltage source, a second transistor having a second source connected to the second voltage source, and a second gate and a second drain connected to the first node, and an amplifier having an input terminal connected to an output terminal of the inverter and configured to output a first voltage from the first voltage or a second voltage from the second voltage source based on or in response to an output of the inverter.

Abstract: An input/output circuit includes a logic unit configured to generate a first signal and a second signal based on data and a first control signal, a driver including a first PMOS transistor having a first gate, a first source that receives a first voltage from a first voltage source, and a first drain, and a first NMOS transistor having a second gate that receives the second signal, a second source that receives a second voltage from a second voltage source less than the first voltage, and a second drain connected to the first drain, a gate-tracking circuit configured to receive the first signal and transfer the received first signal to the first gate of the first PMOS transistor based on a second control signal, and an input/output terminal connected to the first drain and the second drain.

Abstract: An ESD protection SCR device includes an epitaxial layer provided on a P-type semiconductor substrate, the epitaxial layer having the P-type conductivity, element isolation layers provided on the epitaxial layer, the element isolation layers dividing the epitaxial layer into an anode region and a cathode region, a first well of an N-type conductivity, provided in a portion of the epitaxial layer corresponding to the anode region, a first impurity region provided on a surface of the first well, the first impurity region being connected to an anode terminal and having a high concentration P-type conductivity, a second well of the P-type conductivity, provided in a portion of the epitaxial layer corresponding to the cathode region, a second impurity region provided on a surface of the second well, the second impurity region being connected to a cathode terminal and having a high concentration N-type conductivity, and a floating well of the N-type conductivity, buried in the epitaxial layer.

Abstract: An ESD protection SCR device includes an epitaxial layer provided on a P-type semiconductor substrate, the epitaxial layer having the P-type conductivity, element isolation layers provided on the epitaxial layer, the element isolation layers dividing the epitaxial layer into an anode region and a cathode region, a first well of an N-type conductivity, provided in a portion of the epitaxial layer corresponding to the anode region, a first impurity region provided on a surface of the first well, the first impurity region being connected to an anode terminal and having a high concentration P-type conductivity, a second well of the P-type conductivity, provided in a portion of the epitaxial layer corresponding to the cathode region, a second impurity region provided on a surface of the second well, the second impurity region being connected to a cathode terminal and having a high concentration N-type conductivity, and a floating well of the N-type conductivity, buried in the epitaxial layer.

Abstract: An ESD protection SCR device includes a semiconductor substrate, an epitaxial layer, device isolation layers, an n-type well formed in an anode region, a first high concentration p-type impurity region formed on a surface portion of the n-type well, a first high concentration n-type impurity region formed on the surface portion of the n-type well, a p-type well formed in an cathode region, a second high concentration n-type impurity region formed on a surface portion of the p-type well, a second high concentration p-type impurity region formed on a surface portion of the p-type well so as to be spaced apart from the second high concentration n-type impurity region, and a third high-concentration p-type impurity region formed on the surface portion of the p-type well so as to surround a side portion of the second high-concentration n-type impurity region, adjacent to the anode region.

Abstract: An ESD protection SCR device includes a semiconductor substrate, an epitaxial layer, device isolation layers, an n-type well formed in an anode region, a first high concentration p-type impurity region formed on a surface portion of the n-type well, a first high concentration n-type impurity region formed on the surface portion of the n-type well, a p-type well formed in an cathode region, a second high concentration n-type impurity region formed on a surface portion of the p-type well, a second high concentration p-type impurity region formed on a surface portion of the p-type well so as to be spaced apart from the second high concentration n-type impurity region, and a third high-concentration p-type impurity region formed on the surface portion of the p-type well so as to surround a side portion of the second high-concentration n-type impurity region, adjacent to the anode region.

Abstract: A device for protecting a semiconductor device from electrostatic discharge may include a high voltage first conductivity type well formed in a semiconductor substrate. A first stack region may have a first conductivity type drift region, and a first conductivity type impurity region stacked in succession in the high voltage first conductivity type well. A second stack region may have a second conductivity type drift region, and a second conductivity type impurity region stacked in succession in the high voltage first conductivity type well. A device isolating film formed between the first stack region and the second stack region for isolating the first stack region from the second stack region.

Abstract: A hybrid protection circuit may include a stress detection circuit, a clamp device, and an on-time adjustment circuit. The stress detection circuit may output a detection signal that may be activated when a positive ESD event or a positive EOS event occurs. The on-time adjustment circuit may receive a detection signal and output a clamping signal that may be in an active state until charges generated by a positive ESD event or a positive EOS event are discharged. The clamp device may discharge charges induced by an ESD event or an EOS event. Therefore, a hybrid protection circuit may protect the internal core from both an ESD event and an EOS event.

Abstract: A device for protecting a semiconductor device from electrostatic discharge may include a high voltage first conductivity type well formed in a semiconductor substrate. A first stack region may have a first conductivity type drift region, and a first conductivity type impurity region stacked in succession in the high voltage first conductivity type well. A second stack region may have a second conductivity type drift region, and a second conductivity type impurity region stacked in succession in the high voltage first conductivity type well. A device isolating film formed between the first stack region and the second stack region for isolating the first stack region from the second stack region.

Abstract: A hybrid protection circuit may include a stress detection circuit, a clamp device, and an on-time adjustment circuit. The stress detection circuit may output a detection signal that may be activated when a positive ESD event or a positive EOS event occurs. The on-time adjustment circuit may receive a detection signal and output a clamping signal that may be in an active state until charges generated by a positive ESD event or a positive EOS event are discharged. The clamp device may discharge charges induced by an ESD event or an EOS event. Therefore, a hybrid protection circuit may protect the internal core from both an ESD event and an EOS event.