Patents by Inventor Joon Teik Hor

Joon Teik Hor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11663154
    Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: May 30, 2023
    Assignee: Intel Corporation
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Publication number: 20230026906
    Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.
    Type: Application
    Filed: August 12, 2022
    Publication date: January 26, 2023
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Publication number: 20220350769
    Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.
    Type: Application
    Filed: April 15, 2022
    Publication date: November 3, 2022
    Applicant: Intel Corporation
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Patent number: 11442876
    Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Patent number: 11308018
    Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Publication number: 20200409899
    Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Patent number: 10776302
    Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Publication number: 20200244397
    Abstract: Data of different types are received on a plurality of data lanes of a physical link. Particular data is received on at least a portion of the plurality of data lanes, and a stream signal, corresponding to the particular data, is received on another of the lanes of the physical link, where the particular data is of a particular type different from other data previously sent on the plurality of data lanes. The stream signal includes a code component indicating that the particular data is of the particular type and a parity component for use in identifying whether a bit error is present in the stream signal.
    Type: Application
    Filed: September 26, 2015
    Publication date: July 30, 2020
    Inventors: Venkatraman Iyer, Mahesh Wagh, Joon Teik HOR
  • Publication number: 20190347218
    Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.
    Type: Application
    Filed: May 30, 2019
    Publication date: November 14, 2019
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Publication number: 20190227972
    Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Applicant: Intel Corporation
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Patent number: 8250253
    Abstract: Techniques for generating information identifying a next direct memory access (DMA) task to be serviced. In an embodiment, arbitration logic provides a sequence of masking logic to determine, according to a hierarchy of rules, a next task to be serviced by a DMA engine. In certain embodiments, masking logic includes logic to mask information representing pending tasks to be serviced, the masking based on identification of a channel as being a suspended channel and/or a victim channel.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: August 21, 2012
    Assignee: Intel Corporation
    Inventors: Joon Teik Hor, Suryaprasad Kareenahalli
  • Publication number: 20110320645
    Abstract: Techniques for generating information identifying a next direct memory access (DMA) task to be serviced. In an embodiment, arbitration logic provides a sequence of masking logic to determine, according to a hierarchy of rules, a next task to be serviced by a DMA engine. In certain embodiments, masking logic includes logic to mask information representing pending tasks to be serviced, the masking based on identification of a channel as being a suspended channel and/or a victim channel.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Inventors: Joon Teik Hor, Suryaprasad Kareenahalli