Patents by Inventor Joon-Woo Cho
Joon-Woo Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127746Abstract: A light emitting display device includes a display panel including a first pixel group including a plurality of pixels in 2N rows. The light emitting display device further includes a second pixel group disposed subsequent to the first pixel group and including a plurality of pixels in 2N rows. The light emitting display device further includes an emission signal unit including a first emission stage for applying the same first emission signal to the first pixel group and a second emission stage for applying the same second emission signal to the second pixel group. In a first frame, a falling time of the first emission signal and a rising time of the second emission signal are different from each other.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Applicant: LG Display Co., Ltd.Inventors: Jeong Ki KIM, Joon Young PARK, Jae Woo PARK, Sung Min CHO, Hyeong Kyu KIM
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Publication number: 20240087133Abstract: Disclosed are a method for refining a tissue image by removing, from a slide image of a tissue specimen, a tissue specimen region determined to be another tissue specimen, and a computer system performing same. According to one aspect of the present invention, provided is a method for refining a tissue specimen image, comprising the steps of: extracting a plurality of contours corresponding to a plurality of tissue regions included in a tissue specimen image; calculating the center point coordinates of each of the extracted plurality of contours; determining a main tissue contour from among the plurality of contours, on the basis of the center point coordinates of the tissue specimen image and the center point coordinates of each of the plurality of contours; and removing a region corresponding to at least a part of the contours other than the main tissue contour among the plurality of contours.Type: ApplicationFiled: January 19, 2022Publication date: March 14, 2024Inventors: Joon Young CHO, Tae Yeong TWAK, Sun Woo KIM
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Patent number: 11919122Abstract: A substrate processing apparatus includes: a conveyor belt configured to have an outer surface on which a bottom surface of a substrate is seated; and a polishing head unit configured to face an upper surface of the substrate, wherein the polishing head unit includes: a polishing head connected to a driver; a polishing pad configured to face the polishing head; a polishing pad fixing ring disposed between the polishing head and the polishing pad; and a temperature sensor configured to overlap the polishing pad fixing ring and to be spaced apart from the polishing pad fixing ring.Type: GrantFiled: September 29, 2020Date of Patent: March 5, 2024Assignees: SAMSUNG DISPLAY CO., LTD., KCTECH CO., LTD.Inventors: Seung Bae Kang, Sung Hyeon Park, Jung Gun Nam, Joon-Hwa Bae, Kyung Bo Lee, Keun Woo Lee, Woo Jin Cho, Byoung Kwon Choo
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Patent number: 11714122Abstract: A semiconductor device and a method of testing the same are provided. A semiconductor device includes a Design Under Test (DUT), a processing core configured to execute test software to determine an optimum operating voltage of the DUT, and a protection circuit configured to block the transmission of undefined signals generated by the DUT while the processing core executes the test software.Type: GrantFiled: June 4, 2021Date of Patent: August 1, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon Woo Cho, Yun Ju Kwon, Sang Woo Kim
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Publication number: 20210293876Abstract: A semiconductor device and a method of testing the same are provided. A semiconductor device includes a Design Under Test (DUT), a processing core configured to execute test software to determine an optimum operating voltage of the DUT, and a protection circuit configured to block the transmission of undefined signals generated by the DUT while the processing core executes the test software.Type: ApplicationFiled: June 4, 2021Publication date: September 23, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Joon Woo CHO, Yun Ju KWON, Sang Woo KIM
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Patent number: 11054462Abstract: A semiconductor device and a method of testing the same are provided. A semiconductor device includes a Design Under Test (DUT), a processing core configured to execute test software to determine an optimum operating voltage of the DUT, and a protection circuit configured to block the transmission of undefined signals generated by the DUT while the processing core executes the test software.Type: GrantFiled: October 24, 2017Date of Patent: July 6, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Joon Woo Cho, Yun Ju Kwon, Sang Woo Kim
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Patent number: 10769085Abstract: A bus system is provided. A bus system includes a slave functional block and a master functional block. The master functional block transmits a first command to the slave functional block. The slave functional block includes a first bus protector. The first bus protector receives the first command on behalf of the slave functional block and transmits a dummy signal corresponding to the first command to the master functional block in response to the slave functional block being in a state of not being able to receive the first command or not being able to transmit a response signal corresponding to the first command.Type: GrantFiled: April 2, 2018Date of Patent: September 8, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Woo Cho, Yun Ju Kwon, Sang Woo Kim, Woo-Jin Kim
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Patent number: 10587265Abstract: Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a hardware auto clock gating (HWACG) logic configured to provide clock gating of an intellectual property (IP) block; and a memory power controller configured to perform power gating of a memory electrically connected with the IP block, based on the HWACG logic providing the clock gating for the IP block. The HWACG logic includes a first clock source configured to provide a first clock signal; a second clock source configured to receive the first clock signal provided by the first clock source, and provide a second clock signal to the IP block; a first clock control circuit configured to control the first clock source; and a second clock control circuit configured to transmit a clock request to the first clock control circuit, and control the second clock source, based on an operation state of the IP block.Type: GrantFiled: August 21, 2018Date of Patent: March 10, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoo Seok Shon, Sang Woo Kim, Byung Tak Lee, Yun Ju Kwon, Joon-Woo Cho
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Publication number: 20190214989Abstract: Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a hardware auto clock gating (HWACG) logic configured to provide clock gating of an intellectual property (IP) block; and a memory power controller configured to perform power gating of a memory electrically connected with the IP block, based on the HWACG logic providing the clock gating for the IP block. The HWACG logic includes a first clock source configured to provide a first clock signal; a second clock source configured to receive the first clock signal provided by the first clock source, and provide a second clock signal to the IP block; a first clock control circuit configured to control the first clock source; and a second clock control circuit configured to transmit a clock request to the first clock control circuit, and control the second clock source, based on an operation state of the IP block.Type: ApplicationFiled: August 21, 2018Publication date: July 11, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoo Seok SHON, Sang Woo KIM, Byung Tak LEE, Yun Ju KWON, Joon-Woo CHO
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Publication number: 20190102332Abstract: A bus system is provided. A bus system includes a slave functional block and a master functional block. The master functional block transmits a first command to the slave functional block. The slave functional block includes a first bus protector. The first bus protector receives the first command on behalf of the slave functional block and transmits a dummy signal corresponding to the first command to the master functional block in response to the slave functional block being in a state of not being able to receive the first command or not being able to transmit a response signal corresponding to the first command.Type: ApplicationFiled: April 2, 2018Publication date: April 4, 2019Inventors: Joon-Woo Cho, Yun Ju Kwon, Sang Woo Kim, Woo-Jin Kim
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Publication number: 20180217202Abstract: A semiconductor device and a method of testing the same are provided. A semiconductor device includes a Design Under Test (DUT), a processing core configured to execute test software to determine an optimum operating voltage of the DUT, and a protection circuit configured to block the transmission of undefined signals generated by the DUT while the processing core executes the test software.Type: ApplicationFiled: October 24, 2017Publication date: August 2, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Joon Woo CHO, Yun Ju KWON, Sang Woo KIM
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Patent number: 9122802Abstract: Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.Type: GrantFiled: March 18, 2014Date of Patent: September 1, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Woo Cho, Jong Ho Roh, Jae Geun Yun, Sung-Min Hong
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Publication number: 20140201407Abstract: Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.Type: ApplicationFiled: March 18, 2014Publication date: July 17, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon-Woo CHO, Jong Ho ROH, Jae Geun YUN, Sung-Min HONG
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Patent number: 8713233Abstract: Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.Type: GrantFiled: March 17, 2011Date of Patent: April 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Woo Cho, Jong Ho Roh, Jae Geun Yun, Sung-Min Hong
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Patent number: 8193840Abstract: A system timer including a divider unit configured to fractionally divide a first clock signal and output a second clock signal having an asymmetric duty ratio and an interrupt generation unit configured to count a cycle of the second clock signal and output an interrupt signal according to the count.Type: GrantFiled: February 2, 2010Date of Patent: June 5, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Woo Cho, Eui Cheol Lim
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Publication number: 20110276735Abstract: Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.Type: ApplicationFiled: March 17, 2011Publication date: November 10, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon-Woo CHO, Jong Ho ROH, Jae Geun YUN, Sung-Min HONG
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Publication number: 20100207672Abstract: A system timer including a divider unit configured to fractionally divide a first clock signal and output a second clock signal having an asymmetric duty ratio and an interrupt generation unit configured to count a cycle of the second clock signal and output an interrupt signal according to the count.Type: ApplicationFiled: February 2, 2010Publication date: August 19, 2010Inventors: Joon-Woo Cho, Eui Cheol Lim