Patents by Inventor Joon Woo CHOI
Joon Woo CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12207907Abstract: An apparatus for and a method for estimating blood pressure are provided. The apparatus for estimating blood pressure includes: a sensor configured to measure a pulse wave signal from an object; and a processor configured to obtain a mean arterial pressure (MAP) based on the pulse wave signal, configured to classify a phase of the obtained MAP according to at least one classification criterion, and to obtain a systolic blood pressure (SBP) by using an estimation model corresponding to the classified phase of the MAP among estimation models corresponding to respective phases of the MAP.Type: GrantFiled: November 13, 2020Date of Patent: January 28, 2025Assignees: SAMSUNG ELECTRONICS CO., LTD., IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)Inventors: Sang Kon Bae, Joon-Hyuk Chang, Chang Mok Choi, Youn Ho Kim, Jin Woo Choi, Jehyun Kyung, Tae-Jun Park, Joon-Young Yang, Inmo Yeon
-
Publication number: 20250019135Abstract: A sealing structure may include a lid including a first lid face, a second lid face opposite to the first lid face, and a fragile area between the first lid face and the second lid face, a cover including a first cover face facing the second lid face and covering the fragile area and a second cover face opposite to the first cover face, wherein a first distance between the second lid face and the first cover face is substantially equal to or less than a second distance between the first cover face and the second cover face, and a connector configured to connect the lid and the cover.Type: ApplicationFiled: September 30, 2024Publication date: January 16, 2025Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wooram HONG, Hyun Do CHOI, Dal HEO, Youngchun KWON, Hyukju KWON, Gahee KIM, Bosung KIM, Jeonghun KIM, Jin Woo KM, Min Sik PARK, Youngjin PARK, Hyungtae SEO, Won Seok OH, Dongseon LEE, Sangyoon LEE, Jaejun CHANG, Jun Won JANG, Hyunjeong JEON, Joon-Kee CHO, Byung-Kwon CHOI, Won Je CHOI, Younsuk CHOI, Taesin HA
-
Patent number: 12189765Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.Type: GrantFiled: November 21, 2023Date of Patent: January 7, 2025Assignee: SK hynix Inc.Inventors: Joon-Woo Choi, Jeong-Tae Hwang
-
Publication number: 20240086531Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Joon-Woo CHOI, Jeong-Tae HWANG
-
Patent number: 11861000Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.Type: GrantFiled: April 7, 2020Date of Patent: January 2, 2024Assignee: SK hynix Inc.Inventors: Joon-Woo Choi, Jeong-Tae Hwang
-
Patent number: 11200944Abstract: A semiconductor memory apparatus includes a plurality of memory cells. Each memory cell includes a switching element and a storage capacitor. The semiconductor memory apparatus further includes a first word line extended from a part of the plurality of memory cells, a second word line which is enabled after the first word line is enabled in a refresh mode for refreshing data stored in the storage capacitor, a word line control circuit configured to enable and disable the first word line. The word line control circuit comprises at least one switch that couples and decouples the first word line and the second word line.Type: GrantFiled: August 4, 2020Date of Patent: December 14, 2021Assignee: SK hynix Inc.Inventors: Joon Woo Choi, Chang Ki Baek
-
Publication number: 20210042407Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.Type: ApplicationFiled: April 7, 2020Publication date: February 11, 2021Inventors: Joon-Woo CHOI, Jeong-Tae HWANG
-
Publication number: 20200381038Abstract: A semiconductor memory apparatus includes a plurality of memory cells. Each memory cell includes a switching element and a storage capacitor. The semiconductor memory apparatus further includes a first word line extended from a part of the plurality of memory cells, a second word line which is enabled after the first word line is enabled in a refresh mode for refreshing data stored in the storage capacitor, a word line control circuit configured to enable and disable the first word line. The word line control circuit comprises at least one switch that couples and decouples the first word line and the second word line.Type: ApplicationFiled: August 4, 2020Publication date: December 3, 2020Applicant: SK hynix Inc.Inventors: Joon Woo CHOI, Chang Ki BAEK
-
Patent number: 10741240Abstract: A semiconductor memory apparatus includes a word line control circuit configured to enable and disable a word line, wherein the word line control circuit comprises a switch which couples and decouples the word line to and from at least one other word line.Type: GrantFiled: August 14, 2018Date of Patent: August 11, 2020Assignee: SK hynix Inc.Inventors: Joon Woo Choi, Chang Ki Baek
-
Publication number: 20190198086Abstract: A semiconductor memory apparatus includes a word line control circuit configured to enable and disable a word line, wherein the word line control circuit comprises a switch which couples and decouples the word line to and from at least one other word line.Type: ApplicationFiled: August 14, 2018Publication date: June 27, 2019Applicant: SK hynix Inc.Inventors: Joon Woo CHOI, Chang Ki BAEK
-
Patent number: 9875994Abstract: A multi-chip package may include a plurality of semiconductor chips integrated in a single package and sharing one or more command pins. Each of the semiconductor chips may include: a command decoder suitable for decoding a command to generate a buffer enable signal, a mode enable signal, and a mode signal; a data input buffer suitable for buffering data to output internal data, in response to the buffer enable signal and a common test mode signal; a command controller suitable for receiving the mode enable signal to output a test mode enable signal by selectively blocking the mode enable signal based on the internal data and the common test mode signal; and a test controller suitable for generating the common test mode signal and a test mode signal, based on the test mode enable signal and the mode signal.Type: GrantFiled: February 18, 2016Date of Patent: January 23, 2018Assignee: SK Hynix Inc.Inventors: Chang-Ki Baek, Joon-Woo Choi
-
Patent number: 9792230Abstract: A data input circuit of a semiconductor apparatus may include a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner, and a data control block configured to transmit serial test data, which may be input through less than all of the plurality of input/output pads, to the plurality of parallelizing units in response to first and second control signals.Type: GrantFiled: October 14, 2014Date of Patent: October 17, 2017Assignee: SK hynix Inc.Inventors: Joon Woo Choi, Chang Ki Baek
-
Publication number: 20170084580Abstract: A multi-chip package may include a plurality of semiconductor chips integrated in a single package and sharing one or more command pins. Each of the semiconductor chips may include: a command decoder suitable for decoding a command to generate a buffer enable signal, a mode enable signal, and a mode signal; a data input buffer suitable for buffering data to output internal data, in response to the buffer enable signal and a common test mode signal; a command controller suitable for receiving the mode enable signal to output a test mode enable signal by selectively blocking the mode enable signal based on the internal data and the common test mode signal; and a test controller suitable for generating the common test mode signal and a test mode signal, based on the test mode enable signal and the mode signal.Type: ApplicationFiled: February 18, 2016Publication date: March 23, 2017Inventors: Chang-Ki BAEK, Joon-Woo CHOI
-
Patent number: 9286999Abstract: A semiconductor device includes a first input/output (I/O) part buffering command/address (C/A) signals inputted through a first pad part to generate delay address signals, an internal address generator generating a plurality of internal address signals according to a level combination of the delay address signals, and a second I/O part including a plurality of fuses selected by the plurality of internal address signals in a test mode. The plurality of fuses of the second I/O part are programmed according to logic levels of data inputted to the second I/O part through a second pad part to control I/O characteristics of the second I/O part.Type: GrantFiled: April 14, 2015Date of Patent: March 15, 2016Assignee: SK Hynix Inc.Inventors: Joon Woo Choi, Chang Ki Baek
-
Publication number: 20160042772Abstract: A semiconductor device may include a first input/output unit and a second input/output unit. The first input/output unit may operate in synchronization with an internal clock signal to output a first data as a first output data in response to a control signal or to output a transfer data generated from a second data as the first output data in response to the control signal. The second input/output unit may operate in synchronization with the internal clock signal to generate the transfer data while in a test mode. The first output data may be transmitted to a first pad.Type: ApplicationFiled: October 29, 2014Publication date: February 11, 2016Inventors: Joon Woo CHOI, Chang Ki BAEK
-
Publication number: 20160004649Abstract: A data input circuit of a semiconductor apparatus may include a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner, and a data control block configured to transmit serial test data, which may be input through less than all of the plurality of input/output pads, to the plurality of parallelizing units in response to first and second control signals.Type: ApplicationFiled: October 14, 2014Publication date: January 7, 2016Inventors: Joon Woo CHOI, Chang Ki BAEK