Patents by Inventor Joon Woo CHOI

Joon Woo CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12207907
    Abstract: An apparatus for and a method for estimating blood pressure are provided. The apparatus for estimating blood pressure includes: a sensor configured to measure a pulse wave signal from an object; and a processor configured to obtain a mean arterial pressure (MAP) based on the pulse wave signal, configured to classify a phase of the obtained MAP according to at least one classification criterion, and to obtain a systolic blood pressure (SBP) by using an estimation model corresponding to the classified phase of the MAP among estimation models corresponding to respective phases of the MAP.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: January 28, 2025
    Assignees: SAMSUNG ELECTRONICS CO., LTD., IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Sang Kon Bae, Joon-Hyuk Chang, Chang Mok Choi, Youn Ho Kim, Jin Woo Choi, Jehyun Kyung, Tae-Jun Park, Joon-Young Yang, Inmo Yeon
  • Publication number: 20250019135
    Abstract: A sealing structure may include a lid including a first lid face, a second lid face opposite to the first lid face, and a fragile area between the first lid face and the second lid face, a cover including a first cover face facing the second lid face and covering the fragile area and a second cover face opposite to the first cover face, wherein a first distance between the second lid face and the first cover face is substantially equal to or less than a second distance between the first cover face and the second cover face, and a connector configured to connect the lid and the cover.
    Type: Application
    Filed: September 30, 2024
    Publication date: January 16, 2025
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wooram HONG, Hyun Do CHOI, Dal HEO, Youngchun KWON, Hyukju KWON, Gahee KIM, Bosung KIM, Jeonghun KIM, Jin Woo KM, Min Sik PARK, Youngjin PARK, Hyungtae SEO, Won Seok OH, Dongseon LEE, Sangyoon LEE, Jaejun CHANG, Jun Won JANG, Hyunjeong JEON, Joon-Kee CHO, Byung-Kwon CHOI, Won Je CHOI, Younsuk CHOI, Taesin HA
  • Patent number: 12189765
    Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.
    Type: Grant
    Filed: November 21, 2023
    Date of Patent: January 7, 2025
    Assignee: SK hynix Inc.
    Inventors: Joon-Woo Choi, Jeong-Tae Hwang
  • Publication number: 20240086531
    Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Joon-Woo CHOI, Jeong-Tae HWANG
  • Patent number: 11861000
    Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: January 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Joon-Woo Choi, Jeong-Tae Hwang
  • Patent number: 11200944
    Abstract: A semiconductor memory apparatus includes a plurality of memory cells. Each memory cell includes a switching element and a storage capacitor. The semiconductor memory apparatus further includes a first word line extended from a part of the plurality of memory cells, a second word line which is enabled after the first word line is enabled in a refresh mode for refreshing data stored in the storage capacitor, a word line control circuit configured to enable and disable the first word line. The word line control circuit comprises at least one switch that couples and decouples the first word line and the second word line.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: December 14, 2021
    Assignee: SK hynix Inc.
    Inventors: Joon Woo Choi, Chang Ki Baek
  • Publication number: 20210042407
    Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.
    Type: Application
    Filed: April 7, 2020
    Publication date: February 11, 2021
    Inventors: Joon-Woo CHOI, Jeong-Tae HWANG
  • Publication number: 20200381038
    Abstract: A semiconductor memory apparatus includes a plurality of memory cells. Each memory cell includes a switching element and a storage capacitor. The semiconductor memory apparatus further includes a first word line extended from a part of the plurality of memory cells, a second word line which is enabled after the first word line is enabled in a refresh mode for refreshing data stored in the storage capacitor, a word line control circuit configured to enable and disable the first word line. The word line control circuit comprises at least one switch that couples and decouples the first word line and the second word line.
    Type: Application
    Filed: August 4, 2020
    Publication date: December 3, 2020
    Applicant: SK hynix Inc.
    Inventors: Joon Woo CHOI, Chang Ki BAEK
  • Patent number: 10741240
    Abstract: A semiconductor memory apparatus includes a word line control circuit configured to enable and disable a word line, wherein the word line control circuit comprises a switch which couples and decouples the word line to and from at least one other word line.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Joon Woo Choi, Chang Ki Baek
  • Publication number: 20190198086
    Abstract: A semiconductor memory apparatus includes a word line control circuit configured to enable and disable a word line, wherein the word line control circuit comprises a switch which couples and decouples the word line to and from at least one other word line.
    Type: Application
    Filed: August 14, 2018
    Publication date: June 27, 2019
    Applicant: SK hynix Inc.
    Inventors: Joon Woo CHOI, Chang Ki BAEK
  • Patent number: 9875994
    Abstract: A multi-chip package may include a plurality of semiconductor chips integrated in a single package and sharing one or more command pins. Each of the semiconductor chips may include: a command decoder suitable for decoding a command to generate a buffer enable signal, a mode enable signal, and a mode signal; a data input buffer suitable for buffering data to output internal data, in response to the buffer enable signal and a common test mode signal; a command controller suitable for receiving the mode enable signal to output a test mode enable signal by selectively blocking the mode enable signal based on the internal data and the common test mode signal; and a test controller suitable for generating the common test mode signal and a test mode signal, based on the test mode enable signal and the mode signal.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: January 23, 2018
    Assignee: SK Hynix Inc.
    Inventors: Chang-Ki Baek, Joon-Woo Choi
  • Patent number: 9792230
    Abstract: A data input circuit of a semiconductor apparatus may include a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner, and a data control block configured to transmit serial test data, which may be input through less than all of the plurality of input/output pads, to the plurality of parallelizing units in response to first and second control signals.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: October 17, 2017
    Assignee: SK hynix Inc.
    Inventors: Joon Woo Choi, Chang Ki Baek
  • Publication number: 20170084580
    Abstract: A multi-chip package may include a plurality of semiconductor chips integrated in a single package and sharing one or more command pins. Each of the semiconductor chips may include: a command decoder suitable for decoding a command to generate a buffer enable signal, a mode enable signal, and a mode signal; a data input buffer suitable for buffering data to output internal data, in response to the buffer enable signal and a common test mode signal; a command controller suitable for receiving the mode enable signal to output a test mode enable signal by selectively blocking the mode enable signal based on the internal data and the common test mode signal; and a test controller suitable for generating the common test mode signal and a test mode signal, based on the test mode enable signal and the mode signal.
    Type: Application
    Filed: February 18, 2016
    Publication date: March 23, 2017
    Inventors: Chang-Ki BAEK, Joon-Woo CHOI
  • Patent number: 9286999
    Abstract: A semiconductor device includes a first input/output (I/O) part buffering command/address (C/A) signals inputted through a first pad part to generate delay address signals, an internal address generator generating a plurality of internal address signals according to a level combination of the delay address signals, and a second I/O part including a plurality of fuses selected by the plurality of internal address signals in a test mode. The plurality of fuses of the second I/O part are programmed according to logic levels of data inputted to the second I/O part through a second pad part to control I/O characteristics of the second I/O part.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: March 15, 2016
    Assignee: SK Hynix Inc.
    Inventors: Joon Woo Choi, Chang Ki Baek
  • Publication number: 20160042772
    Abstract: A semiconductor device may include a first input/output unit and a second input/output unit. The first input/output unit may operate in synchronization with an internal clock signal to output a first data as a first output data in response to a control signal or to output a transfer data generated from a second data as the first output data in response to the control signal. The second input/output unit may operate in synchronization with the internal clock signal to generate the transfer data while in a test mode. The first output data may be transmitted to a first pad.
    Type: Application
    Filed: October 29, 2014
    Publication date: February 11, 2016
    Inventors: Joon Woo CHOI, Chang Ki BAEK
  • Publication number: 20160004649
    Abstract: A data input circuit of a semiconductor apparatus may include a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner, and a data control block configured to transmit serial test data, which may be input through less than all of the plurality of input/output pads, to the plurality of parallelizing units in response to first and second control signals.
    Type: Application
    Filed: October 14, 2014
    Publication date: January 7, 2016
    Inventors: Joon Woo CHOI, Chang Ki BAEK