Patents by Inventor Joon-Yeon Kim

Joon-Yeon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240195293
    Abstract: A circuit for preventing power imbalance of a resonance-type power converter is proposed. The circuit may include a rectifier converting input alternating current (AC) into direct current (DC) and frequency-controlled first and second resonant converter modules configured to receive an output voltage of the rectifier divided into two stages. The circuit may further include a controller outputting a first frequency command for controlling a frequency of a pulse width modulation (PWM) signal supplied to a switching element of a first switching unit of the first resonant converter module. The circuit may further include a frequency compensator compensating for the first frequency command and then outputting a second frequency command for controlling a frequency of a PWM signal supplied to a switching element of a second switching unit of the second resonant converter module, so as to eliminate power imbalance between the first and second resonant converter modules.
    Type: Application
    Filed: December 4, 2023
    Publication date: June 13, 2024
    Inventors: Dong Myoung JOO, Jun Hyuk CHOI, Joon Sung PARK, Jin Hong KIM, Byong Jo HYON, Yong Su NOH, Sang Min PARK, Dae Yeon HWANG, Hyoung Kyu YANG, Poo Reum JANG
  • Patent number: 11936969
    Abstract: A camera module includes: a first substrate on which an image sensor configured to convert an optical signal incident through a lens module into an electrical signal is disposed and a first connection terminal is disposed; a second substrate spaced apart from the first substrate and including a second connection terminal formed in a position facing the first connection terminal; and a terminal connector electrically connecting the first connection terminal and the second connection terminal to each other and configured to maintain a preset distance between the first substrate and the second substrate. In the camera module, the terminal connector includes: a connecting member including a first connection portion, a second connection portion, and a deformable portion; and a support member configured to maintain the preset distance between the first substrate and the second substrate.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Se Yeon Hwang, Hyun Sang Kwak, Yeo Ok Jeon, Joon Woo Gi, Seok Hwan Kim
  • Patent number: 11930361
    Abstract: A method of a wearable device displaying icons is provided. The method includes displaying a plurality of circular icons comprising a first circular icon located in a center area of a touch display in a first size and a second circular icon located outside of the center area of the touch display in a second size smaller than the first size, and based on a direction of a touch input received on the touch display, moving the plurality of circular icons such that the first circular icon is moved to a first position located outside of the center area of the touch display and the second circular icon is moved from a second position located outside the center area of the touch display to the center area of the touch display and enlarged in size from the second size to the first size.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-kyu Seo, Young-joon Choi, Ji-yeon Kwak, Hyun-jin Kim, Yeo-jun Yoon
  • Patent number: 9651577
    Abstract: A pogo pin may include a housing, a resilient connecting member and a switching unit. The housing may be arranged between a printed circuit board (PCB) and a probing head. The resilient connecting member may be arranged in the housing to electrically connect the PCB with the probing head. The switching unit may be provided in the housing to selectively cut off an electrical connection between the PCB and the probing head. Thus, because the PCB may not require additional switching substrates, the PCB may have a small size so that the probe card may also have a small size. A semiconductor device may be manufactured using the probe card.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Ho Joo, Yu-Kyum Kim, Joon-Yeon Kim
  • Publication number: 20150070038
    Abstract: A pogo pin may include a housing, a resilient connecting member and a switching unit. The housing may be arranged between a printed circuit board (PCB) and a probing head. The resilient connecting member may be arranged in the housing to electrically connect the PCB with the probing head. The switching unit may be provided in the housing to selectively cut off an electrical connection between the PCB and the probing head. Thus, because the PCB may not require additional switching substrates, the PCB may have a small size so that the probe card may also have a small size. A semiconductor device may be manufactured using the probe card.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 12, 2015
    Inventors: Sung-Ho JOO, Yu-Kyum KIM, Joon-Yeon KIM
  • Publication number: 20140253165
    Abstract: A probe card includes a first circuit substrate electrically connected to a tester, the first circuit substrate having a first size, a second circuit substrate on a lower surface of the first circuit substrate and electrically connected to the first circuit substrate, the second circuit substrate having a second size smaller than the first size, a probe head under the second circuit substrate and electrically connected to the second circuit substrate, the probe head including a plurality of probes in contact with terminals of a device under test (DUT), and a probe holder under the first circuit substrate and supporting the probe head.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 11, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yu-Kyum KIM, Joon-Yeon KIM, Sung-Ho JOO
  • Publication number: 20120229159
    Abstract: A test interface board includes a wiring group, a plurality of contact portions, and a control device. The wiring group includes a main wire operatively coupled to a channel of a tester, and a plurality of sub-wires operatively coupled to the main wire. The plurality of contact portions are operatively coupled to the plurality of sub-wires, and contact first electrodes of a plurality of semiconductor devices. The control device includes a plurality of switching devices operatively coupled to the plurality of sub-wires, a memory configured to store an identification number, and a controller configured to open and close the plurality of switching devices in response to a control signal corresponding to the identification number from among a plurality of control signals.
    Type: Application
    Filed: February 24, 2012
    Publication date: September 13, 2012
    Inventors: Joon-yeon KIM, Cheol-jong WOO, Chang-hyun CHO, Hyung-soon KIM
  • Patent number: 8049681
    Abstract: A waveform generator capable of generating a square wave and a ramp wave using one switching element is provided. A waveform generator includes a first transistor having a drain electrode, a gate electrode, and a source electrode. A first resistor and a first diode are coupled at a common node between a first input terminal and the gate electrode. A second resistor is coupled between the gate electrode and a second input terminal. A first capacitor is coupled between the drain electrode and the common node between the first resistor and the first diode.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: November 1, 2011
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Hak-Cheol Yang, Joon-Yeon Kim, Yon-Goo Park, Jong-Ki Choi
  • Patent number: 7701235
    Abstract: Substrate test probing equipment having a force-receiving pattern for a probe card and a forcing part for a test head, and methods of using the same, in which with the force-receiving pattern for the probe card and the forcing part for the test head, thermal expansion and contraction of the probe card can be suppressed when the semiconductor substrate is being tested at high and low temperatures. To this end, to substrate test probing equipment having a substrate mover, a probe card, and a test head is prepared, in which the test head has a forcing part and the probe card has a force-receiving plate. A semiconductor substrate is placed on the substrate mover to be electrically connected with the probe card. The semiconductor substrate is electrically tested by the probe card and the test head. When the semiconductor substrate is being tested, the forcing part of the test head is brought into contact with the force-receiving pattern of the probe card.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hyun Cho, Joon-Yeon Kim, Sang-Gu Kang, Sung-Mo Kang, Sang-Kyu Yoo
  • Patent number: 7616176
    Abstract: A plasma display and driving method thereof. A median electrode is formed between X and Y electrodes for receiving sustain pulse voltages, and a reset waveform and a scan pulse voltage are applied to the median electrode. A short gap discharge is performed between the X electrode and the median electrode during the initial interval of a sustain interval, and a long gap discharge is performed between the X and Y electrodes during the normal sustain interval to thus perform a stable discharge. The X and Y electrode drivers are realized through comparable circuits since the waveforms applied to the X and Y electrodes are substantially symmetric.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: November 10, 2009
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jeong-Doo Yi, Jeong-Nam Kim, Tae-Woo Kim, Joon-Yeon Kim, Su-Yong Chae
  • Patent number: 7612738
    Abstract: A plasma display device includes first to fourth transistors and a plurality of first electrodes. A first terminal of a first capacitor is connected to a power supply supplying a voltage. A second terminal of a second capacitor connected to a second terminal of the first capacitor is connected to a ground terminal. A first diode is connected to the first electrodes through a first inductor and a fifth transistor, which forms a voltage rising path. A second diode is connected to the first electrodes through a second inductor and a sixth transistor, which forms a voltage falling path. A third diode is connected to the third transistor and the second diode, which forms a voltage sustaining path during a voltage rising period. A fourth diode is connected to the second transistor and the first diode, which forms a voltage sustaining path of a voltage falling period.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: November 3, 2009
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Hak-Cheol Yang, Joon-Yeon Kim, Jong-Ki Choi, Hyun-Gu Heo, Yong-Jin Jeong, Suk-Chin Sakong, Sung-Soo Hong, Chung-Wook Roh, Sang-Kyoo Han, Won-Seok Nam, Yon-Goo Park
  • Patent number: 7592978
    Abstract: A method for driving a plasma display panel (PDP) and for safely erasing wall charges in an erase period. The PDP includes a middle (M) electrode formed between an X electrode and a Y electrode. A sustain discharge pulse voltage is periodically applied to the X electrode and the Y electrode in a pulse train fashion. In addition, a reset waveform, a scan pulse voltage, and a sustain discharge voltage are applied to the middle electrode. Moreover, to prevent a strong discharge, an erase waveform is applied to the M electrode in the erase period while the X and Y electrodes are biased with the same voltage level. Alternatively, to prevent a strong discharge, an erase waveform (a gradually rising waveform) is applied to the X electrode in the erase period while the M and Y electrodes are biased with the same voltage level (a ground voltage).
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: September 22, 2009
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Joon-Yeon Kim
  • Publication number: 20090121978
    Abstract: A plasma display device includes a plurality of scan lines for selecting a plurality of discharge cells and extending in a row direction. The plasma display device sequentially applies a scan pulse to the plurality of scan lines. The plasma display device calculates a data similarity ratio of two adjacent scan lines by using subfield data of each discharge cell disposed on the two adjacent scan lines among the plurality of scan lines, and overlaps the scan pulses applied to the two adjacent scan lines when the data similarity ratio of two adjacent scan lines is greater than a predetermined ratio.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 14, 2009
    Inventors: Hak-Cheol Yang, Joon-Yeon Kim, Yon-Goo Park, Jong-Ki Choi
  • Publication number: 20090121748
    Abstract: A waveform generator capable of generating a square wave and a ramp wave using one switching element is provided. A waveform generator includes a first transistor having a drain electrode, a gate electrode, and a source electrode. A first resistor and a first diode are coupled at a common node between a first input terminal and the gate electrode. A second resistor is coupled between the gate electrode and a second input terminal. A first capacitor is coupled between the drain electrode and the common node between the first resistor and the first diode.
    Type: Application
    Filed: October 9, 2008
    Publication date: May 14, 2009
    Inventors: Hak-Cheol Yang, Joon-Yeon Kim, Yon-Goo Park, Jong-Ki Choi
  • Publication number: 20080297185
    Abstract: A multi probe card unit, a probe test device including the multi probe card unit, and methods of fabricating and using the same are provided. The multi probe card unit may include at least one probe card including a first plurality of probes on a first surface of the at least one probe card and a second plurality of probes on a second surface of the at least one probe card.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 4, 2008
    Inventors: Sang-gu Kang, Chang-Hyun Cho, Sung-mo Kang, Sang-kyo Yoo, Joon-yeon Kim
  • Publication number: 20080252327
    Abstract: Substrate test probing equipment having a force-receiving pattern for a probe card and a forcing part for a test head, and methods of using the same, in which with the force-receiving pattern for the probe card and the forcing part for the test head, thermal expansion and contraction of the probe card can be suppressed when the semiconductor substrate is being tested at high and low temperatures. To this end, to substrate test probing equipment having a substrate mover, a probe card, and a test head is prepared, in which the test head has a forcing part and the probe card has a force-receiving plate. A semiconductor substrate is placed on the substrate mover to be electrically connected with the probe card. The semiconductor substrate is electrically tested by the probe card and the test head. When the semiconductor substrate is being tested, the forcing part of the test head is brought into contact with the force-receiving pattern of the probe card.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 16, 2008
    Inventors: Chang-Hyun Cho, Joon-Yeon Kim, Sang-Gu Kang, Sung-Mo Kang, Sang-Kyu Yoo
  • Publication number: 20080117122
    Abstract: A method for driving a plasma display device (PDP) during subfields of a frame including a first subfield. The PDP includes scan lines corresponding to first and second display regions, address lines crossing the scan lines, and first and second discharge cells respectively defined by the first display regions and the address lines and by the second display regions and the address lines. The method includes: selecting a first non-light emitting cell from among first light emitting cells of the first discharge cells during a first address period of the first subfield; selecting a second non-light emitting cell from among second light emitting cells of the second discharge cells during a second address period of the first subfield; and sustain-discharging the first and second light emitting cells during a first period previous to the first address period and a second period previous to the second address period, respectively.
    Type: Application
    Filed: April 4, 2007
    Publication date: May 22, 2008
    Inventors: Joon-Yeon Kim, Hak-Cheol Yang
  • Publication number: 20080100607
    Abstract: A driver circuit for a plasma display panel is disclosed. The circuit drives the panel using low supply voltage to reduce cost. The circuit sequentially charges and discharges capacitors to provide signals to the panel during reset, address, and sustain periods.
    Type: Application
    Filed: September 26, 2007
    Publication date: May 1, 2008
    Inventor: Joon-Yeon Kim
  • Publication number: 20080088531
    Abstract: A plasma display device includes first to fourth transistors and a plurality of first electrodes. A first terminal of a first capacitor is connected to a power supply supplying a voltage. A second terminal of a second capacitor connected to a second terminal of the first capacitor is connected to a ground terminal. A first diode is connected to the first electrodes through a first inductor and a fifth transistor, which forms a voltage rising path. A second diode is connected to the first electrodes through a second inductor and a sixth transistor, which forms a voltage falling path. A third diode is connected to the third transistor and the second diode, which forms a voltage sustaining path during a voltage rising period. A fourth diode is connected to the second transistor and the first diode, which forms a voltage sustaining path of a voltage falling period.
    Type: Application
    Filed: March 28, 2007
    Publication date: April 17, 2008
    Inventors: Hak-Cheol Yang, Joon-Yeon Kim, Jong-Ki Choi, Hyun-Gu Heo, Yong-Jin Jeong, Suk-Chin Sakong, Sung-Soo Hong, Chung-Wook Roh, Sang-Kyoo Han, Won-Seok Nam, Yon-Goo Park
  • Publication number: 20080068366
    Abstract: In a plasma display device, a driver circuit and a method of driving that reduces costs by eliminating the need for high voltage transistors. A first terminal of an inductor is coupled to a plurality of first electrodes. A first terminal of a first capacitor is coupled to the first terminal of the inductor, a second terminal of the first capacitor is coupled to the plurality of first electrodes, a first terminal of a second capacitor is coupled to the first terminal of the inductor, and a second terminal of the second capacitor is coupled to the plurality of first electrodes. In addition, a resonance path for varying a voltage at the plurality of first electrodes is formed between a node of the first and second capacitors and the plurality of first electrodes.
    Type: Application
    Filed: August 23, 2007
    Publication date: March 20, 2008
    Inventors: Joon-Yeon Kim, Yong-Jin Jeong