Abstract: A vehicular air conditioning system includes a cooling heat exchanger and a heating heat exchanger sequentially installed on an internal flow path of an air conditioning case to cool and heat an air blown from a blower, a plurality of air discharge ports configured to discharge cold air and hot air passing through the cooling heat exchanger and the heating heat exchanger into a passenger room, a first bypass flow path configured to allow the air blown from the blower to bypass to an upstream side of the heating heat exchanger before passing through the cooling heat exchanger, and a first opening/closing door configured to open and close the first bypass flow path.

Abstract: A vehicular air conditioning system includes: a refrigerant circulation line including first and second evaporators through which refrigerant can flow in a cooling mode, and first and second expansion valves configured to depressurize and expand the refrigerant introduced into each of the first and second evaporators; and refrigerant flow control part provided in front of the first evaporator and the first expansion valve and configured to control refrigerant flow. The first evaporator is used for cooling rear seat region of a passenger room and the refrigerant flow control part is configured to supply and block the refrigerant with respect to the first evaporator and the first expansion valve and is configured to block the refrigerant when the cooling governed by the first evaporator is controlled in a turn-off mode and supply the refrigerant to the first evaporator and the first expansion valve depending on the on/off condition of the cooling governed by the second evaporator.

Abstract: A vehicle air conditioner for minimizing the leakage of air through a dual blocking structure between upper and lower flow paths, and having a dual blocking structure. An air-conditioning case having an inner air flow path is divided into an upper flow path and a lower flow path. A heat exchanger for cooling and a heat exchanger for heating are provided in the air flow path of the air-conditioning case. A member having through-holes is disposed downstream of the heat exchanger for heating in the flow direction of air and allows the air that has passed through the heat exchanger for heating to pass therethrough. The member having through-holes has a horizontal member dividing the upper flow path from the lower flow path. A leakage-preventing means is overlapped with the horizontal member so as to prevent the air in the upper flow path and the lower flow path from mixing.

Abstract: The present disclosure relates to a phase synchronization device, and more specifically, to a stochastic RF phase synchronization system (SRFPS) for correcting a phase error of a recovered signal on the basis of an RF signal received through a receiver. The phase synchronization device according to an exemplary embodiment of the present disclosure includes: a sampling unit for outputting a sampling value by sampling a recovered signal based on a predetermined threshold voltage value; a phase shift control unit for calculating a cost value for the recovered signal by using a histogram function generated on the basis of the sampling value, and determining an optimal phase offset value on the basis of the cost value; and a phase shift unit for shifting the phase of an oscillation signal according to the optimal phase offset value.

Abstract: The present disclosure relates to a phase synchronization device, and more specifically, to a stochastic RF phase synchronization system (SRFPS) for correcting a phase error of a recovered signal on the basis of an RF signal received through a receiver. The phase synchronization device according to an exemplary embodiment of the present disclosure includes: a sampling unit for outputting a sampling value by sampling a recovered signal based on a predetermined threshold voltage value; a phase shift control unit for calculating a cost value for the recovered signal by using a histogram function generated on the basis of the sampling value, and determining an optimal phase offset value on the basis of the cost value; and a phase shift unit for shifting the phase of an oscillation signal according to the optimal phase offset value.

Abstract: The present invention relates to a waveguide for transmission of electromagnetic wave signals. According to one aspect of the invention, there is provided a waveguide for transmission of electromagnetic wave signals, comprising: a dielectric part comprising two or more dielectrics having different permittivity; and a conductor part surrounding at least a part of the dielectric part.

Abstract: The present invention relates to a waveguide for transmission of electromagnetic wave signals and a chip-to-chip interface apparatus comprising the same. According to one aspect of the invention, there is provided a waveguide for transmission of electromagnetic wave signals, comprising: a dielectric part; and a conductor part surrounding at least a part of the dielectric part, wherein a signal of a first frequency band is transmitted through the dielectric part, and a signal of a second frequency band lower than the first frequency band is transmitted through the conductor part.

Abstract: The present invention relates to a microstrip-waveguide transition for transmission of electromagnetic wave signals. According to one aspect of the invention, there is provided a microstrip-waveguide transition for transmission of electromagnetic wave signals, comprising: a feeding part for providing an electromagnetic wave signal to be transmitted through the waveguide; and a ground part formed at a predetermined interval from the feeding part, wherein the microstrip and the waveguide are coupled alongside each other along a length direction of the waveguide, and wherein a distance between the feeding part and the ground part in a direction perpendicular to the length direction of the waveguide is greater as it is closer to the waveguide.

Abstract: The present invention relates to a microstrip-waveguide transition for transmission of electromagnetic wave signals. According to one aspect of the invention, there is provided a microstrip-waveguide transition for transmission of electromagnetic wave signals, comprising: a feeding part for providing an electromagnetic wave signal to be transmitted through the waveguide; and a ground part formed at a predetermined interval from the feeding part, wherein the microstrip and the waveguide are coupled alongside each other along a length direction of the waveguide, and wherein a distance between the feeding part and the ground part in a direction perpendicular to the length direction of the waveguide is greater as it is closer to the waveguide.

Abstract: The present invention relates to a waveguide for transmission of electromagnetic wave signals and a chip-to-chip interface apparatus comprising the same. According to one aspect of the invention, there is provided a waveguide for transmission of electromagnetic wave signals, comprising: a dielectric part; and a conductor part surrounding at least a part of the dielectric part, wherein a signal of a first frequency band being a relatively higher frequency band is transmitted through the dielectric part, and a signal of a second frequency band being a relatively lower frequency band is transmitted through the conductor part.

Abstract: The present invention relates to a waveguide for transmission of electromagnetic wave signals. According to one aspect of the invention, there is provided a waveguide for transmission of electromagnetic wave signals, comprising: a dielectric part comprising two or more dielectrics having different permittivity; and a conductor part surrounding at least a part of the dielectric part.

Abstract: The present invention relates to a microstrip circuit and a chip-to-chip interface apparatus comprising the same. According to one aspect of the invention, there is provided a microstrip circuit. The microstrip circuit includes a feeding line providing a signal, a probe being connected to one end of the feeding line, and a patch emitting the signal to a waveguide. The patch is disposed in a layer opposite to a layer in which the feeding line and the probe are disposed, with a core substrate being positioned therebetween. At least one of length of the probe, thickness of the core substrate, and permittivity of the core substrate is determined based on bandwidth of a transition between the microstrip circuit and the waveguide.

Abstract: The CDR (Clock Data Recovery) device may include at least one or more CDR channels configured to receive input data stream; and a global clock generator configured to provide a frequency locked clock to each of the at least one or more CDR channels, wherein each of the at least one or more CDR channels creates a reference clock signal for the global clock generator.

Abstract: The present invention relates to a microstrip circuit and a chip-to-chip interface apparatus comprising the same. According to one aspect of the invention, there is provided a microstrip circuit. The microstrip circuit includes a feeding line providing a signal, a probe being connected to one end of the feeding line, and a patch emitting the signal to a waveguide. The patch is disposed in a layer opposite to a layer in which the feeding line and the probe are disposed, with a core substrate being positioned therebetween. At least one of length of the probe, thickness of the core substrate, and permittivity of the core substrate is determined based on bandwidth of a transition between the microstrip circuit and the waveguide.

Abstract: The CDR (Clock Data Recovery) device may include at least one or more CDR channels configured to receive input data stream; and a global clock generator configured to provide a frequency locked clock to each of the at least one or more CDR channels, wherein each of the at least one or more CDR channels creates a reference clock signal for the global clock generator.

Abstract: The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)-based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jitter-tolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for low-power applications since a phase shifter in the data path, which is one of the most power-hungry blocks in conventional DPLL designs, is not required.

Abstract: Exemplary embodiments of the present invention relate to an internal jitter tolerance tester. The internal jitter tolerance tester may include a digital loop filter consisting of a cyclic accumulator which accumulates a phase detector's output, a gain multiplier, an internal accumulated jitter generator (or an internal sinusoid jitter generator), and a phase rotator (or DCO) controller. The internal accumulated jitter generator may include a PRBS generator, a digital loop filter, an accumulator, and a gain controller. The accumulated jitter generator also may be replaced with the internal sinusoid jitter generator. The internal sinusoid jitter generator may include a counter, a sinusoid jitter profile lookup table, and a gain controller.

Abstract: Exemplary embodiments of the present invention relate to an internal jitter tolerance tester. The internal jitter tolerance tester may include a digital loop filter consisting of a cyclic accumulator which accumulates a phase detector's output, a gain multiplier, an internal accumulated jitter generator (or an internal sinusoid jitter generator), and a phase rotator (or DCO) controller. The internal accumulated jitter generator may include a PRBS generator, a digital loop filter, an accumulator, and a gain controller. The accumulated jitter generator also may be replaced with the internal sinusoid jitter generator. The internal sinusoid jitter generator may include a counter, a sinusoid jitter profile lookup table, and a gain controller.

Abstract: Exemplary embodiments of the present invention relate to a clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor. The Kalman gain extractor includes an off chip digital processor which receives a phase update information from the CDR outputs an estimated optimum Kalman gain obtained by extracting the standard deviation of step sizes of the accumulation jitter from the power spectral density (PSD) of the phase update information, and a on chip digital loop filter consists of a cyclic accumulator which accumulates the phase detector's output, a gain multiplier and a phase interpolator (or DCO) controller. The off chip digital processor includes a storage register, a fast Fourier transform (FFT) processor and an optimum Kalman gain estimator. The storage register stores the phase update information, from which the FFT processor extracts the PSD of the absolute input jitter.

Abstract: Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response.