Patents by Inventor Joon-yong Choi
Joon-yong Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220413713Abstract: A method for operating a memory includes: performing an error check operation; detecting N bad sections during the error check operation, where N is an integer equal to or greater than 1; stopping the error check operation in response to the detecting of the N bad sections; transferring information on the N bad sections to a memory controller; and resuming the error check operation in response to the transferring of the information on the N bad sections to a memory controller.Type: ApplicationFiled: November 4, 2021Publication date: December 29, 2022Inventor: Joon Yong CHOI
-
Patent number: 11314650Abstract: A data processing system includes a host processor, a processor suitable for processing a task instructed by the host processor, a memory, shared by the host processor and the processor, that is suitable for storing data processed by the host processor and the processor, respectively, and a memory controller suitable for checking whether a stored data processed by the host processor and the processor are reused, and for sorting and managing the stored data as a first data and a second data based on the check result.Type: GrantFiled: December 18, 2019Date of Patent: April 26, 2022Assignee: SK hynix Inc.Inventors: Won-Ha Choi, Joon-Yong Choi
-
Patent number: 11221909Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.Type: GrantFiled: February 26, 2020Date of Patent: January 11, 2022Assignee: SK hynix Inc.Inventors: Kang-Sub Kwak, Young-Jun Yoon, Joon-Yong Choi
-
Patent number: 11216331Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.Type: GrantFiled: February 26, 2020Date of Patent: January 4, 2022Assignee: SK hynix Inc.Inventors: Kang-Sub Kwak, Young-Jun Yoon, Joon-Yong Choi
-
Patent number: 11200111Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.Type: GrantFiled: February 26, 2020Date of Patent: December 14, 2021Assignee: SK hynix Inc.Inventors: Kang-Sub Kwak, Young-Jun Yoon, Joon-Yong Choi
-
Publication number: 20200293451Abstract: A data processing system includes a host processor, a processor suitable for processing a task instructed by the host processor, a memory, shared by the host processor and the processor, that is suitable for storing data processed by the host processor and the processor, respectively, and a memory controller suitable for checking whether a stored data processed by the host processor and the processor are reused, and for sorting and managing the stored data as a first data and a second data based on the check result.Type: ApplicationFiled: December 18, 2019Publication date: September 17, 2020Inventors: Won-Ha CHOI, Joon-Yong CHOI
-
Publication number: 20200192748Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.Type: ApplicationFiled: February 26, 2020Publication date: June 18, 2020Inventors: Kang-Sub KWAK, Young-Jun YOON, Joon-Yong CHOI
-
Publication number: 20200192746Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.Type: ApplicationFiled: February 26, 2020Publication date: June 18, 2020Applicant: SK hynix Inc.Inventors: Kang-Sub KWAK, Young-Jun YOON, Joon-Yong CHOI
-
Publication number: 20200192747Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.Type: ApplicationFiled: February 26, 2020Publication date: June 18, 2020Inventors: Kang-Sub KWAK, Young-Jun YOON, Joon-Yong CHOI
-
Patent number: 10606689Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.Type: GrantFiled: April 12, 2018Date of Patent: March 31, 2020Assignee: SK hynix Inc.Inventors: Kang-Sub Kwak, Young-Jun Yoon, Joon-Yong Choi
-
Publication number: 20180300200Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second dataType: ApplicationFiled: April 12, 2018Publication date: October 18, 2018Inventors: Kang-Sub KWAK, Young-Jun YOON, Joon-Yong CHOI
-
Patent number: 10064597Abstract: The present invention relates to a head and neck simulation phantom device for simulating the head and neck of a body, the phantom device including: a flat type first plate having a first insertion groove formed on one surface thereof; a flat type second plate disposed to come into contact with the other surface of the first plate and having a second insertion groove formed on the contacted surface with the other surface of the first plate in such a manner as to correspond to the first insertion groove; and a plurality of teeth simulants inserted into the first insertion groove and the second insertion groove and for simulating the teeth of the body.Type: GrantFiled: April 2, 2015Date of Patent: September 4, 2018Assignee: The Catholic University of Korea Industry—Academic Cooperation FoundationInventors: Tae Suk Suh, Min Young Lee, Ji Yeon Park, Jeong Woo Lee, Joon Yong Choi, Sang Won Kang, Hae Jin Park
-
Patent number: 9864540Abstract: A system may include a processor and a memory. The processor and the memory may communicate with each other in a balanced code multiphase signal transmission scheme. The processor and the memory may include interface circuits, respectively. The interface circuit may generate data based on multiphase symbols. For example, the interface circuit may include a decoding block which generates 5-bit data based on 2 symbols which are successively inputted.Type: GrantFiled: September 30, 2015Date of Patent: January 9, 2018Assignee: SK hynix Inc.Inventor: Joon Yong Choi
-
Publication number: 20170019202Abstract: A system may include a processor and a memory. The processor and the memory may communicate through a wire bus. The memory may include a receiver configured to generate phase symbols based on states of the wire bus, and a decoding block configured to generate data based on a number of phase symbols successively inputted.Type: ApplicationFiled: September 30, 2015Publication date: January 19, 2017Inventor: Joon Yong CHOI
-
Publication number: 20170017432Abstract: A system may include a processor and a memory. The processor and the memory may communicate with each other in a balanced code multiphase signal transmission scheme. The processor and the memory may include interface circuits, respectively. The interface circuit may generate data based on multiphase symbols. For example, the interface circuit may include a decoding block which generates 5-bit data based on 2 symbols which are successively inputted.Type: ApplicationFiled: September 30, 2015Publication date: January 19, 2017Inventor: Joon Yong CHOI
-
Publication number: 20170000452Abstract: The present invention relates to a head and neck simulation phantom device for simulating the head and neck of a body, the phantom device including: a flat type first plate having a first insertion groove formed on one surface thereof; a flat type second plate disposed to come into contact with the other surface of the first plate and having a second insertion groove formed on the contacted surface with the other surface of the first plate in such a manner as to correspond to the first insertion groove; and a plurality of teeth simulants inserted into the first insertion groove and the second insertion groove and for simulating the teeth of the body.Type: ApplicationFiled: April 2, 2015Publication date: January 5, 2017Inventors: TAE SUK SUH, MIN YOUNG LEE, JI YEON PARK, JEONG WOO LEE, JOON YONG CHOI, SANG WON KANG, HAE JIN PARK
-
Patent number: 8416617Abstract: A semiconductor device includes phase-change memory cells and an access circuit. The access circuit generates a plurality of bitwise comparison signals indicating different comparison events for respective write and read bit groups. At least a portion of the write data is then written to the phase-change memory cells according to a number of activated comparison signals for each comparison event, as well as according to a ratio of a set current pulse width and a reset current pulse width as applied to the of phase-change memory cells.Type: GrantFiled: March 28, 2011Date of Patent: April 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Yong Choi, Hoi Ju Chung
-
Patent number: 8310891Abstract: The present invention relates to a resistance variable memory device, and more particularly, to a resistance variable memory device capable of preventing an effect of coupling noise. The resistance variable memory device includes: a memory cell connected to a bit line; a precharge circuit precharging the bit line in response to a precharge signal; a bias circuit providing a bias voltage to the bit line in response to a bias signal; and a control logic controlling the precharge signal and the bias signal. The control logic provides the bias signal to the bias circuit at a precharge interval. Accordingly, the resistance variable memory device according to the present invention can prevent an effect coupling noise.Type: GrantFiled: October 6, 2009Date of Patent: November 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: HoJung Kim, Joon-Yong Choi
-
Patent number: 8305806Abstract: A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.Type: GrantFiled: March 17, 2010Date of Patent: November 6, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Yong Choi, Byunggil Choi, Yu Hwan Ro, Yong-Jun Lee
-
Patent number: 8250289Abstract: A semiconductor memory device includes a memory cell array and the memory cell array includes: a plurality of memory blocks and at least one setting unit. The at least one setting unit stores a location and a size of a boot data storage region within the plurality of memory blocks that stores boot data. The at least one setting units may include a register for setting usage of each memory block as a boot block. The semiconductor device may be a phase-change memory.Type: GrantFiled: March 11, 2009Date of Patent: August 21, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yu-hwan Ro, Kwang-ho Kim, Kwang-jin Lee, Joon-yong Choi