Abstract: A flash memory device is provided. The flash memory device is disposed on a substrate, a channel layer made of a two-dimensional material, sources and drains disposed at both ends of the channel layer, a tunneling insulating layer having a first dielectric constant and a tunneling insulating layer disposed on the channel layer, a floating gate made of a two-dimensional material, a blocking insulating layer disposed on the floating gate and having a second dielectric constant greater than the first dielectric constant, and an upper gate disposed on the blocking insulating layer.

Abstract: Provided is a neuromorphic system for synaptic learning in a spiking neural network (SNN)-based neuromorphic array structure. Control blocks including a post-synaptic neuron, which generates a post-neuron spike, are disposed on output lines of a synapse array to implement a spike timing dependent plasticity (STDP) operation such that synaptic learning can be stably implemented in an SNN neuromorphic array. Also, a lateral inhibition circuit may be added. When a post-neuron spike is generated by an STDP control block connected to any one output line, the lateral inhibition circuit inhibits STDP control blocks connected to other output lines from generating spikes. Accordingly, learning selectivity can be improved, and thus the performance of an STDP algorithm can be improved.

Abstract: Provided are an autonomous driving system and a correction learning method for autonomous driving. The autonomous driving system includes a sensor configured to collect and output data required for autonomous driving, a first processor configured to output autonomous driving data on the basis of data input from the sensor, a second processor configured to output a driving data adjustment value on the basis of differences between the data input from the sensor, the autonomous driving data input from the first processor, and driving data input from driving by a human driver, and a driving part configured to perform driving on the basis of the autonomous driving data output from the first processor and the driving data adjustment value output from the second processor.

Abstract: The present disclosure relates to a nonlinearity compensation circuit for a memristive device. The circuit according to an embodiment includes at least one power source unit to apply an input pulse; a modulation unit connected to the at least one power source unit to adjust a pulse width of an update pulse to be applied to the memristive device; and the memristive device to which the modulated update pulse is applied.

Abstract: This disclosure relates to exact sun-tracking devices by the principle of exact sun-following by independent 2-DOF, which says if the daily rotation axis is installed on a ground structure in parallel with the earth's rotation axis and the elevation angle axis is mounted perpendicularly to the daily rotation axis then the two rotational degrees of freedom are independent of each other. This property makes a separate intermittent control with a forward half-step setting very efficient and energy-saving. A control system by a wire loop driving mechanism has several advantages, holding the structure securely, relieving a motor weight from the over-structure, and allowing a simple economic control with self-locking. Three structural types are categorized: a long shaft type, a tip-tilt type, and a tension structure type. An array sun-tracking device with an efficient wire loop actuating mechanism illustrates a preferred sun power generation system for general and industrial applications.

Abstract: An artificial neuron device according to an embodiment of the present disclosure includes a first resistor connected between an input terminal and a first node; a capacitor connected between the first node and a ground terminal; a threshold switch connected between the first node and a second node; and a second resistor connected between the second node and the ground terminal, wherein, when an input voltage of a certain level is applied to the input terminal by time, a membrane potential occurs at the first node and a spike current flows through the second node. According to present disclosure, the artificial neuron device expresses the Integrate-and-Fire function, the rate coding ability, the SFA characteristics, and the chaotic activity of the biological neuron, and therefore may be widely used for the artificial neuron network device, the large-scale brain-inspired computing system, and the artificial intelligence (AI) system.

Abstract: A flash memory device is provided. The flash memory device is disposed on a substrate, a channel layer made of a two-dimensional material, sources and drains disposed at both ends of the channel layer, a tunneling insulating layer having a first dielectric constant and a tunneling insulating layer disposed on the channel layer, a floating gate made of a two-dimensional material, a blocking insulating layer disposed on the floating gate and having a second dielectric constant greater than the first dielectric constant, and an upper gate disposed on the blocking insulating layer.

Abstract: A nano-oscillator device includes a switching element configured to be switched to an ON state at a threshold voltage or above and switched to an OFF state below a holding voltage; and a load element connected to the switching element in series. In the nano-oscillator device, vibration characteristics are implemented by using a switching element and a load element connected thereto in series. Also, the oscillation frequency of the output waveform of the oscillator may be adjusted in real time according to a gate voltage by using a field effect transistor serving as a load element. Using a synchronization characteristic in which the oscillation frequency and phase are locked with respect to an external input, it is possible to implement a computing system based on a network in which a plurality of oscillator devices are coupled.

Abstract: A neuromorphic device includes: a neuron block unit including a plurality of neurons; a synapse block unit including a plurality of synapses; and a topology block unit including a plurality of parallel Look-Up Table (LUT) modules including pre and post neuron elements configured with addresses of a presynaptic neuron and a postsynaptic neuron. Each of the plurality of neurons has an intrinsic address, each of the plurality of synapses has an intrinsic address. The parallel LUT module is partitioned based on a first synapse address among synapse addresses, and each of the partitions is indexed based on a second synapse address among the synapse addresses.

Abstract: Provided is a method of operating a neuron in a neuromorphic system. The method includes evaluating a membrane potential value at a corresponding time when receiving an input spike, time-modulating a synaptic weight of the membrane potential value and converting the time-modulated synaptic weight into a membrane potential value at a reference time, and generating an output spike when the membrane potential value at the reference time exceeds a certain threshold value. The membrane potential value at the reference time is represented by a floating point number including a predetermined bit of exponent and mantissa, and the floating point number includes time information. The method further includes accessing a memory and scanning a neural state variable when a timer is updated to “0” to update the neural state variable to an updated value at a reference time.

Abstract: Embodiments of inventive concepts relate to a neuromorphic circuit including a flash memory-based spike regulator capable of generating a stable spike signal with a small number of devices. The neuromorphic circuit may generate a simple and stable spike signal using a flash memory-based spike regulator. Therefore, it is possible to implement a semiconductor neuromorphic circuit at low power and low cost by using the spike regulator of the present invention. Example embodiments of inventive concepts provide a neuromorphic circuit comprising a control signal generator for generating a control signal for generating a pulse signal; and a spike regulator for generating a spike signal in response to the control signal.

Abstract: A neuromorphic circuit according to example embodiments of inventive concepts includes a first neuron array including a plurality of neuron circuits generating a spike signal; a first synapse array including a plurality of first synapse circuits to process and output the spike signal transmitted from the first neuron array; a second synapse array including a plurality of second synapse circuits; a first connecting block positioned between the first synapse array and the second synapse array and connecting the first synapse array and the second synapse array in response to a control signal; and a control logic to generate the control signal. The neuromorphic circuit may easily expand the size of the synapse element array to a desired size by using a connecting block.

Abstract: An embodiment of the present disclosure discloses a method of process variation compensating through activation value adjustment of an analog binarized neural network circuit that may recover a decrease in recognition rate performance up to an almost perfect level, even if a binarized neural network is implemented as an analog circuit such that recognition rate performance is decreased due to process variation.

Abstract: An artificial neuron device according to an embodiment of the present disclosure includes a first resistor connected between an input terminal and a first node; a capacitor connected between the first node and a ground terminal; a threshold switch connected between the first node and a second node; and a second resistor connected between the second node and the ground terminal, wherein, when an input voltage of a certain level is applied to the input terminal by time, a membrane potential occurs at the first node and a spike current flows through the second node. According to present disclosure, the artificial neuron device expresses the Integrate-and-Fire function, the rate coding ability, the SFA characteristics, and the chaotic activity of the biological neuron, and therefore may be widely used for the artificial neuron network device, the large-scale brain-inspired computing system, and the artificial intelligence (AI) system.

Abstract: Most vibration generators that use rotating eccentric masses of prior arts have disadvantages in controlling vibration magnitude such as stopping equipment, adjusting intermittently, or limitation on control range. In the present invention to continuously change the direction of a generated vibration force or its magnitude, the principle of synthesizing simple harmonic motions by phase shifting is used and two methods, called a mechanical phase shifting and a motor speed controlled phase shifting, are provided. A mechanical phase shifting device includes an angle adjusting plate to change the phases of two eccentric mass rotators and two pairs of gears and links for a reverse rotation of eccentric masses. A motor speed controlled phase shifting is enabled by acceleration and deceleration of a motor. A moment generator comprises two sets of eccentric mass vibrators connected by extending shafts between them and can be used for industry shakers, stabilizer's for floating bodies, and so on.

Abstract: A forest fire smoke detection method using random forest classification is provided. In the method, a first reference value is set. For consecutively captured frames, images between the frames are compared, each block, in which a number of pixels, motions of which have been identified, is equal to or greater than the first reference value, is set as a candidate block, and a keyframe is selected. The selected keyframe is compared with at least one frame previous to the keyframe and then a plurality of feature vectors are extracted from the candidate blocks. The extracted feature vectors are learned using different random forest algorithms. Probabilities output to terminal nodes for classes are accumulated, and two first cumulative probability histograms are generated. The two first cumulative probability histograms are averaged, and then a second cumulative probability histogram is generated. A detected state of each candidate block is determined.

Abstract: A forest fire smoke detection method using random forest classification is provided. In the method, a first reference value is set. For consecutively captured frames, images between the frames are compared, each block, in which a number of pixels, motions of which have been identified, is equal to or greater than the first reference value, is set as a candidate block, and a keyframe is selected. The selected keyframe is compared with at least one frame previous to the keyframe and then a plurality of feature vectors are extracted from the candidate blocks. The extracted feature vectors are learned using different random forest algorithms. Probabilities output to terminal nodes for classes are accumulated, and two first cumulative probability histograms are generated. The two first cumulative probability histograms are averaged, and then a second cumulative probability histogram is generated. A detected state of each candidate block is determined.

Abstract: A nonvolatile memory includes a plurality of N-bit multi-level cell (MLC) memory cells and a controller. The plurality of N-bit MLC memory cells are for storing N pages of data, each of the MLC memory cells programmable into any one of 2N threshold voltage distributions, where N is a positive number. The controller is configured to program the N pages of data into the MLC memory cells, and to execute a partial interleave process in which the N pages of data are divided into M page groups, where M is a positive number and where each page group includes at least one of the N pages of data, and in which each of the M page groups is applied to an error correction code (ECC) circuit to generate parity bits for the respective M page groups, where a bit-error rate (BER) among the pages within each of the M groups is equalized by the partial interleave process.

Abstract: A voltage generator is provided. The voltage generator includes a voltage pump and a voltage controller. The voltage pump generates a target voltage using a clock signal. The voltage controller compares a temporary voltage input from the voltage pump with a reference voltage to generate a control signal controlling the voltage pump. The voltage controller includes a string of a plurality of resistors connected in series to change a level of the temporary voltage to a voltage level of a corresponding comparison voltage. When the plurality of resistors are in a string, a resistance of a resistor closest to one end of the string is greater than resistances of other resistors of the string. The voltage controller may further include a jumping unit controlling connection or disconnection of two arbitrary nodes among first to n-th nodes (where n is a natural number) defined as connection points of the adjacent resistors of the string.

Abstract: A nonvolatile memory device including a memory cell; a word line coupled to the memory cell; a drive line; a switch coupled between the word line and the drive line, and configured to electrically connect the word line and the drive line; and a voltage generator coupled to the drive line and configured to charge the drive line to a precharge voltage. The precharge voltage is higher than a bias voltage applied to the word line during a corresponding operation on the memory cell.