Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

Abstract: An apparatus for estimating blood pressure includes: a photoplethysmogram (PPG) sensor configured to measure a PPG signal from an object; a force sensor configured to measure a force signal acting between the object and the PPG sensor; and a processor configured to (i) divide a predetermined blood pressure range into a plurality of classes, (ii) input the measured PPG signal and the measured force signal into a blood pressure estimation model to obtain the probability values for each of the classes, and (iii) estimate blood pressure based on the obtained probability values for the respective classes.

Abstract: According to an aspect, a WPE-based dereverberation apparatus using virtual acoustic channel expansion based on a deep neural network includes a signal reception unit for receiving as input a first speech signal through a single channel microphone, a signal generation unit for generating a second speech signal by applying a virtual acoustic channel expansion algorithm based on a deep neural network to the first speech signal and a dereverberation unit for removing reverberation of the first speech signal and generating a dereverberated signal from which the reverberation has been removed by applying a dual-channel weighted prediction error (WPE) algorithm based on a deep neural network to the first speech signal and the second speech signal.

Abstract: According to an aspect, a WPE-based dereverberation apparatus using virtual acoustic channel expansion based on a deep neural network includes a signal reception unit for receiving as input a first speech signal through a single channel microphone, a signal generation unit for generating a second speech signal by applying a virtual acoustic channel expansion algorithm based on a deep neural network to the first speech signal and a dereverberation unit for removing reverberation of the first speech signal and generating a dereverberated signal from which the reverberation has been removed by applying a dual-channel weighted prediction error (WPE) algorithm based on a deep neural network to the first speech signal and the second speech signal.

Abstract: An apparatus for estimating bio-information is disclosed. The apparatus may include: a pulse wave sensor configured to measure a pulse wave signal from an object; a force sensor configured to obtain a force signal by measuring an external force exerted onto the force sensor; and a processor configured to obtain a first input value, a second input value, and a third input value based on the pulse wave signal and the force signal, to extract a feature vector by inputting the first input value, the second input value, and the third input value into a first neural network model, and to obtain the bio-information by inputting the feature vector into a second neural network model.

Abstract: An apparatus for and a method for estimating blood pressure are provided. The apparatus for estimating blood pressure includes: a sensor configured to measure a pulse wave signal from an object; and a processor configured to obtain a mean arterial pressure (MAP) based on the pulse wave signal, configured to classify a phase of the obtained MAP according to at least one classification criterion, and to obtain a systolic blood pressure (SBP) by using an estimation model corresponding to the classified phase of the MAP among estimation models corresponding to respective phases of the MAP.

Abstract: Disclosed herein are an apparatus and method for recognizing a voice speaker. The apparatus for recognizing a voice speaker includes a voice feature extraction unit configured to extract a feature vector from a voice signal inputted through a microphone; and a speaker recognition unit configured to calculate a speaker recognition score by selecting a reverberant environment from multiple reverberant environment learning data sets based on the feature vector extracted by the voice feature extraction unit and to recognize a speaker by assigning a weight depending on the selected reverberant environment to the speaker recognition score.

Abstract: Disclosed herein are an apparatus and method for recognizing a voice speaker. The apparatus for recognizing a voice speaker includes a voice feature extraction unit configured to extract a feature vector from a voice signal inputted through a microphone; and a speaker recognition unit configured to calculate a speaker recognition score by selecting a reverberant environment from multiple reverberant environment learning data sets based on the feature vector extracted by the voice feature extraction unit and to recognize a speaker by assigning a weight depending on the selected reverberant environment to the speaker recognition score.

Abstract: Disclosed herein is an online certification mark publication system. The online certification mark publication system includes: a certification mark registration unit configured to register and store a certification mark; an object construction unit configured to accept a registration of an object from a publisher terminal, to also accept a registration of a certification mark assigned to the registered object, and to set hierarchy between registered objects; a module generation unit configured to generate a certification mark module; and a module request processing unit configured to, when a request for a certification mark is received from the certification mark module inserted into the online page, transmit the certification mark of the published object and information about an inheritable certification mark in response to the request, wherein the certification mark is inherited based on the hierarchy between the objects.

Abstract: An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.

Abstract: An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.

Abstract: An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.

Abstract: A thin film transistor substrate includes: pluralities of gate lines and data lines arranged to define a plurality of pixel regions, and a plurality of thin film transistors formed on the pixel regions in such a manner as to include first and second thin film transistors connected to the same gate line and the pixel regions adjacent to each other. Each of the first and second thin film transistors includes: a gate electrode connected to the gate line; a semiconductor layer formed on the gate line in an octagon shape; a source electrode connected to the data line; and a drain electrode formed in an opposite shape to the source electrode.

Abstract: An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.

Abstract: An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.

Abstract: An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.

Abstract: A thin film transistor substrate includes: pluralities of gate lines and data lines arranged to define a plurality of pixel regions, and a plurality of thin film transistors formed on the pixel regions in such a manner as to include first and second thin film transistors connected to the same gate line and the pixel regions adjacent to each other. Each of the first and second thin film transistors includes: a gate electrode connected to the gate line; a semiconductor layer formed on the gate line in an octagon shape; a source electrode connected to the data line; and a drain electrode formed in an opposite shape to the source electrode.

Abstract: An array substrate for a liquid crystal display device includes a data line formed on a substrate including a pixel region; a source electrode extending from the data line; a drain electrode separated from the source electrode; a pixel electrode contacting the drain electrode and formed of a transparent conductive material in the pixel region; an organic semiconductor layer on the source and drain electrodes; a first gate insulating layer of an organic insulating material on the organic semiconductor layer; a second gate insulting layer of an inorganic insulating material on entire surface of the substrate including the first gate insulating layer; a gate line formed on the second gate insulating layer and crossing the data line to define the pixel region; and a gate electrode on the second gate insulating layer extending from the gate line and corresponding to the organic semiconductor layer.

Abstract: The present disclosure relates to a horizontal electric field type liquid crystal display device having the horizontal electric fields over the pixel electrodes and the common electrodes which are disposed on the same level plane, and a method for manufacturing the same. The horizontal electric field type liquid crystal display device comprising: a substrate; a gate line and a data line crossing each other with a gate insulating layer therebetween, and defining a pixel area on the substrate; a thin film transistor formed where the gate line and the data line is crossing; a pixel electrode contacting the thin film transistor on the gate insulating layer; a common electrode disposed in parallel with the pixel electrode having a predetermined distance; and a passivation layer covering whole surface of the substrate including the pixel electrode and the common electrode.

Abstract: An array substrate for a liquid crystal display device includes a gate line on a substrate; a gate insulating layer on the gate line; a data line crossing the gate line; a gate electrode connected to the gate line; an active layer on the gate insulating layer and overlapping the gate electrode; first and second ohmic contact layers on the active layer, the first and second ohmic contact layers spaced apart from each other by a first distance; first and second barrier patterns spaced apart from each other by the first distance and on the first and second ohmic contact layers, respectively. The active layer is exposed through the first and second barrier patterns; source and drain electrodes spaced apart from each other by a second distance greater than the first distance and on the first and second barrier patterns, respectively.