Abstract: A rotation angle detecting method includes detecting a first rotation angle based on a first measured magnetic value received from a first hall element, detecting a first magnetic value received from a second hall element corresponding to the first detected rotation angle, adjusting a gain based on a first difference value between a second measured magnetic value received from the second hall element, in response to one of the magnetic pieces being rotated at the first rotation angle, and the first magnetic value, redetecting a second rotation angle by applying the gain to the first magnetic value and redetecting a second magnetic value received from the second hall element, corresponding to the second rotation angle, and outputting the second rotation angle as a confirmed rotation angle in response to a second difference value between the second magnetic value and the second measured magnetic value becoming less than a delta value.

Abstract: A rotation angle detecting method includes detecting a first rotation angle based on a first measured magnetic value received from a first hall element, detecting a first magnetic value received from a second hall element corresponding to the first detected rotation angle, adjusting a gain based on a first difference value between a second measured magnetic value received from the second hall element, in response to one of the magnetic pieces being rotated at the first rotation angle, and the first magnetic value, redetecting a second rotation angle by applying the gain to the first magnetic value and redetecting a second magnetic value received from the second hall element, corresponding to the second rotation angle, and outputting the second rotation angle as a confirmed rotation angle in response to a second difference value between the second magnetic value and the second measured magnetic value becoming less than a delta value.

Abstract: A slew rate boost circuit for an output buffer and an output buffer circuit for a source driver having the same are provided. In an output buffer including a pull-up unit providing a buffer output signal in a first level by receiving a buffer input signal and performing pull-up operation and a pull-down unit providing a buffer output signal in a second level having opposite phase from the first level by receiving the buffer input signal and performing pull-down operation, the slew rate boost circuit includes a first comparator generating a first boost signal to boost pull-up operation of the pull-up unit of the output buffer by inputting a first input signal and a second input signal and a second comparator generating a second boost signal to boost pull-down operation of the pull-down unit of the output buffer by inputting the first input signal and the second input signal.

Abstract: A slew rate boost circuit for an output buffer and an output buffer circuit for a source driver having the same are provided. In an output buffer including a pull-up unit providing a buffer output signal in a first level by receiving a buffer input signal and performing pull-up operation and a pull-down unit providing a buffer output signal in a second level having opposite phase from the first level by receiving the buffer input signal and performing pull-down operation, the slew rate boost circuit includes a first comparator generating a first boost signal to boost pull-up operation of the pull-up unit of the output buffer by inputting a first input signal and a second input signal and a second comparator generating a second boost signal to boost pull-down operation of the pull-down unit of the output buffer by inputting the first input signal and the second input signal.

Abstract: A semiconductor memory device having a uniform bit line sensing margin time independent on an external voltage variation, includes: a memory cell coupled to a bit line and a word line; an amplifier for amplifying an electric potential of the bit line; a first control signal generator to which an external voltage is supplied for activating the word line; and a second control signal generator to which a core voltage is supplied for controlling an execution of the amplifier by receiving the first control signal.

Abstract: An I/O compression circuit for a semiconductor memory device operates in a same data compress mode to transmit identical data to all compressed data buses and a different data compress mode to transmit different data to adjacent compressed data buses.

Abstract: A semiconductor memory device having a uniform bit line sensing margin time independent on an external voltage variation, includes: a memory cell coupled to a bit line and a word line; an amplifier for amplifying an electric potential of the bit line; a first control signal generator to which an external voltage is supplied for activating the word line; and a second control signal generator to which a core voltage is supplied for controlling an execution of the amplifier by receiving the first control signal.

Abstract: An I/O compression circuit for a semiconductor memory device operates in a same data compress mode to transmit identical data to all compressed data buses and a different data compress mode to transmit different data to adjacent compressed data buses.