Patents by Inventor Joong Chan SHIN

Joong Chan SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10204825
    Abstract: A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Ryul Lee, Joong Chan Shin, Dong Jun Lee, Ho Ouk Lee, Ji Min Choi, Ji Young Kim, Chan Sic Yoon, Chang Hyun Cho
  • Publication number: 20180158718
    Abstract: A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region.
    Type: Application
    Filed: August 2, 2017
    Publication date: June 7, 2018
    Inventors: DONG RYUL LEE, Joong Chan SHIN, Dong Jun LEE, Ho Ouk LEE, Ji Min CHOI, Ji Young KIM, Chan Sic YOON, Chang Hyun CHO