Patents by Inventor Joong Chan SHIN

Joong Chan SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250107109
    Abstract: Disclosed are a memory device and a manufacturing method thereof. The disclosed memory device may include a first substrate structure including a plurality of sense amplifiers (S/A) and a peripheral circuit unit, a second substrate structure bonded to a first surface side of the first substrate structure and including a first cell block including a plurality of first memory cells and a plurality of first bit lines, and a third substrate structure bonded to a second surface side of the first substrate structure and including a second cell block including a plurality of second memory cells and a plurality of second bit lines, wherein each of the plurality of first bit lines and each of the plurality of second bit lines may be commonly connected to each of the plurality of sense amplifiers (S/A).
    Type: Application
    Filed: October 18, 2023
    Publication date: March 27, 2025
    Inventors: Cheol Seong Hwang, Joong Chan Shin
  • Publication number: 20250081445
    Abstract: A semiconductor memory device includes a bit line extending in a first direction on a substrate, an active pattern on the bit line, a word line on a first sidewall of the active pattern and extending in a second direction, a back gate electrode on a second sidewall of the active pattern and extending in the second direction, a gate isolation pattern on the first sidewall of the active pattern and including a low-k pattern extending in the second direction, and a data storage pattern connected to the second surface of the active pattern. The word line is between the active pattern and the gate isolation pattern, and a vertical distance between the bit line and the word line is greater than a vertical distance between the bit line and the low-k pattern.
    Type: Application
    Filed: May 10, 2024
    Publication date: March 6, 2025
    Inventors: Bo Won Yoo, Seok Han Park, Keun Ui Kim, Yu Jin Kim, Joong Chan Shin, Gyu Hwan Oh, Eun Suk Jang, Jin Woo Han
  • Publication number: 20250048622
    Abstract: A semiconductor memory device may include includes a bit line and a back gate strap line extending on a substrate, an active pattern on the bit line and the back gate strap line, a word line on a first side wall of the active pattern, a back gate electrode on a second side wall of the active pattern and connected to the back gate strap line, a data storage pattern connected to a face of the active pattern, and a word line contact plug connected to the word line. A first face of the back gate electrode and a first face of the word line may face the bit line and the back gate strap line. The first face of the back gate electrode may be connected to the back gate strap line. A second face of the word line may be connected to the word line contact plug.
    Type: Application
    Filed: March 11, 2024
    Publication date: February 6, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyun Geun CHOI, Kyung Hwan KIM, Joong Chan SHIN
  • Patent number: 10204825
    Abstract: A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Ryul Lee, Joong Chan Shin, Dong Jun Lee, Ho Ouk Lee, Ji Min Choi, Ji Young Kim, Chan Sic Yoon, Chang Hyun Cho
  • Publication number: 20180158718
    Abstract: A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region.
    Type: Application
    Filed: August 2, 2017
    Publication date: June 7, 2018
    Inventors: DONG RYUL LEE, Joong Chan SHIN, Dong Jun LEE, Ho Ouk LEE, Ji Min CHOI, Ji Young KIM, Chan Sic YOON, Chang Hyun CHO