Abstract: A memory module includes a plurality of ranks that each include a first pin group and a second pin group for receiving external pin signals, and a rank selecting unit included in each of the plurality of ranks, the rank selecting unit configured to output different rank pin signals to each rank by using signals of the first pin group.

Abstract: A semiconductor memory device includes a plurality of memory cell matrixes each of which contains plural memory cell arrays whose number is lager than 2n and smaller than 2n+1, n being a natural number. The semiconductor memory device includes normal memory cell arrays including 2m numbers of memory cell arrays of the plurality of memory cell matrixes, m being a bit of addresses, wherein a data access operation is performed on normal memory cells in the normal memory cell arrays as normal word lines corresponding to the normal memory cells are activated in response to the addresses, and additional redundancy memory cell arrays in the plurality of memory cell matrixes, wherein repair-expected memory cells in the normal memory cell arrays are replaced with the additional redundancy memory cell arrays as redundancy word lines corresponding to the additional redundancy memory cells are activated in response to the addresses corresponding to the repair-expected memory cells.

Abstract: A semiconductor memory includes a cell mat configured to include a plurality of memory cells to which a first bit line pair or a second bit line pair is connected; a sense amplifier configured to amplify a positive sensing line and a negative sensing line in response to a first bit line equalize signal; a column selecting unit configured to connect the positive sensing line and the negative sensing line to a first data bus and a second data bus, respectively, in response to a column selection signal; and a share control unit configured to connect the positive sensing line and a positive first bit line of the first bit line pair or a positive second bit line of the second bit line pair in response to a second bit line equalize signal, a positive share control signal and a negative share control signal.

Abstract: A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.

Abstract: The disclosure relates to a system for controlling devices and information on a network by hand gestures, and more particularly, to a system for controlling devices and information on a network by hand gestures in which a device or a file to be controlled is selected by a user and a display device is pointed so that information and data can be shared and that various devices can be coupled to each other easily and can be controlled easily. The system for controlling devices and information on a network by hand gestures can remarkably improve the interaction between various input and display devices and a user under a ubiquitous computing environment.

Abstract: A semiconductor memory includes a cell mat configured to include a plurality of memory cells to which a first bit line pair or a second bit line pair is connected; a sense amplifier configured to amplify a positive sensing line and a negative sensing line in response to a first bit line equalize signal; a column selecting unit configured to connect the positive sensing line and the negative sensing line to a first data bus and a second data bus, respectively, in response to a column selection signal; and a share control unit configured to connect the positive sensing line and a positive first bit line of the first bit line pair or a positive second bit line of the second bit line pair in response to a second bit line equalize signal, a positive share control signal and a negative share control signal.

Abstract: An apparatus and method for separating and connecting a main camera and a sub camera in a portable terminal are provided. The portable terminal includes a main camera for receiving a main clock signal from a main chip and transmitting a main camera pixel clock signal to the main chip in response to the main clock signal, a sub camera for receiving the main clock signal from the main chip and transmitting a sub camera pixel clock signal to the main chip in response to the main clock signal, and a switch for configuring a path from the main chip to at least one of the main camera and the sub camera.

Abstract: An intelligent computing device agent system for auto recognition of a computing environment of multi-user and optimum information exchange configuration is provided. In the computing device agent system automatically detects the user's computing environment and intelligently makes network access configuration and an information exchange type required between interacting computing devices identical to each other, so that fast, convenient interaction is carried out without complex network configuring or multi-step environment configuring for information exchange.

Abstract: A graphic user interface, an input/output computing apparatus for intuitive interfacing, and a method of interfacing are disclosed. The input/output computing apparatus for intuitive interfacing with a user, includes an input unit to detect one of a plurality of predetermined motions of the user and generate a signal corresponding to the detected predetermined motion, and a controller to carry out an operation corresponding to the signal and generate a control signal to display the result corresponding to the operation.

Abstract: A memory module includes a plurality of ranks that each include a first pin group and a second pin group for receiving external pin signals, and a rank selecting unit included in each of the plurality of ranks, the rank selecting unit configured to output different rank pin signals to each rank by using signals of the first pin group.

Abstract: Provided is an input/output line sharing apparatus of a semiconductor memory device. In this apparatus, a global input/output line is shared by a data line signal and a test mode signal, and an input/output line between test mode signals is shared. The apparatus comprises a global input/output line, a first control signal generating unit configured to generate a test mode control signal from a test mode register set signal, a multiplexer configured to output a signal selected from a data line signal and a test mode signal to the global input/output line in response to the test mode control signal, and a latch unit configured to store the test mode signal outputted from the global input/output line in response to the test mode control signal.

Abstract: Disclosed is a delay locked loop circuit (DLL) used for DDR SDRAM. The DLL provides a fast locking function. In particular, the DLL detects the level of a frequency and performs the fast locking function, thereby realizing a high integrated memory device having a reduced area of a delay part used in order to synchronize a phase of an external clock signal with a phase of an internal clock.

Abstract: A register-controlled delay locked loop (RDLL) circuit for area reduction, includes a first clock buffer for generating a falling clock signal, which is activated at a rising edge of an inverted external clock signal, a second clock buffer for generating a rising clock signal, which is activated at a rising edge of an external clock signal, a clock multiplexer for outputting a single clock signal made by combining the falling clock signal and the rising clock signal, a delay line for delaying the single clock signal to generate a delayed single clock signal, and a controller for controlling the delay line so as to adjust amount of delay of the single clock signal.

Abstract: A register-controlled delay locked loop (RDLL) circuit for area reduction, includes a first clock buffer for generating a falling clock signal, which is activated at a rising edge of an inverted external clock signal, a second clock buffer for generating a rising clock signal, which is activated at a rising edge of an external clock signal, a clock multiplexer for outputting a single clock signal made by combining the falling clock signal and the rising clock signal, a delay line for delaying the single clock signal to generate a delayed single clock signal, and a controller for controlling the delay line so as to adjust amount of delay of the single clock signal.

Abstract: A delay locked loop in accordance with the present invention includes: a first delay delaying an external clock signal; a first pulse generator receiving an output from the first delay, and generating a first input signal in a short-pulse shape; a second delay delaying an inverted external clock signal; a second pulse generator receiving an output from the second delay, and generating a second input signal in a short-pulse shape; a direction control unit generating first and second control signals in order to control a forward or backward delay of the first input signal or the second input signal in accordance with a level of the external clock signal; and a delay chain consisting of a plurality of unit delays having first and second inverters, and delaying the first input signal or the second input signal in the forward and backward directions through the first and second inverters in accordance with the first and second control signals outputted from the direction control unit.