Patents by Inventor Joong Shik Shin
Joong Shik Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10680007Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.Type: GrantFiled: March 23, 2018Date of Patent: June 9, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Jun Shin, Hyun Mog Park, Joong Shik Shin
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Patent number: 10651197Abstract: A semiconductor device comprises a lower conductive layer on a substrate. A conductive line is on the lower conductive layer. A buried trench in the conductive line is provided. A supporter which is on the conductive line and extends in the buried trench is provided. A stack structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked is on the supporter. A channel structure passing through the stack structure, the supporter, and the conductive line is provided. An isolation trench passing through the stack structure, the supporter, and the conductive line is provided.Type: GrantFiled: November 15, 2018Date of Patent: May 12, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Jun Hong, Ee Jou Kim, Joong Shik Shin
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Patent number: 10515819Abstract: A semiconductor device includes a substrate having a first region and a second region, the first region including memory cells, and the second region including transistors for driving the memory cells, and device isolation regions disposed within the substrate to define active regions of the substrate. The active regions include a first guard active region surrounding the first region, a second guard active region surrounding a portion of the second region, and at least one dummy active region disposed between the first guard active region and the second guard active region.Type: GrantFiled: December 18, 2017Date of Patent: December 24, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hoon Park, Joong Shik Shin, Byoung Il Lee, Jong Ho Woo, Eun Taek Jung, Jun Ho Cha
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Publication number: 20190355740Abstract: A semiconductor device comprises a lower conductive layer on a substrate. A conductive line is on the lower conductive layer. A buried trench in the conductive line is provided. A supporter which is on the conductive line and extends in the buried trench is provided. A stack structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked is on the supporter. A channel structure passing through the stack structure, the supporter, and the conductive line is provided. An isolation trench passing through the stack structure, the supporter, and the conductive line is provided.Type: ApplicationFiled: November 15, 2018Publication date: November 21, 2019Inventors: Sang Jun Hong, Ee Jou Kim, Joong Shik Shin
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Publication number: 20190148399Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.Type: ApplicationFiled: August 28, 2018Publication date: May 16, 2019Inventors: Eun-Taek Jung, Joong-Shik Shin, Byung-Kwan You
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Publication number: 20190115366Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.Type: ApplicationFiled: December 6, 2018Publication date: April 18, 2019Inventors: BYOUNG IL LEE, Joong Shik Shin, Dong Seog Eun, Kyung Jun Shin, Hyun Kook Lee
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Patent number: 10204919Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.Type: GrantFiled: August 31, 2016Date of Patent: February 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung Il Lee, Joong Shik Shin, Dong Seog Eun, Kyung Jun Shin, Hyun Kook Lee
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Publication number: 20190027490Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.Type: ApplicationFiled: March 23, 2018Publication date: January 24, 2019Inventors: Seung Jun SHIN, Hyun Mog PARK, Joong Shik SHIN
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Publication number: 20190013206Abstract: A semiconductor device includes a substrate having a first region and a second region, the first region including memory cells, and the second region including transistors for driving the memory cells, and device isolation regions disposed within the substrate to define active regions of the substrate. The active regions include a first guard active region surrounding the first region, a second guard active region surrounding a portion of the second region, and at least one dummy active region disposed between the first guard active region and the second guard active region.Type: ApplicationFiled: December 18, 2017Publication date: January 10, 2019Inventors: Ji Hoon PARK, Joong Shik SHIN, BYOUNG IL LEE, Jong Ho WOO, Eun Taek JUNG, Jun Ho CHA
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Publication number: 20170294388Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate linesare spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.Type: ApplicationFiled: January 9, 2017Publication date: October 12, 2017Inventors: Young-Bae YOON, Joong-Shik SHIN, Kwang-Ho KIM, Hyun-Mog PARK
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Publication number: 20170170191Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.Type: ApplicationFiled: August 31, 2016Publication date: June 15, 2017Inventors: BYOUNG IL LEE, JOONG SHIK SHIN, DONG SEOG EUN, KYUNG JUN SHIN, HYUN KOOK LEE
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Patent number: 9240458Abstract: Provided is a fabricating method of a nonvolatile memory. The fabricating method includes forming a plurality of gates extending in a first direction on a substrate to be adjacent to each other, forming a gap-fill layer filling at least a portion of a space between the plurality of gates, forming a supporter pattern supporting the plurality of gates on the plurality of gates and the gap-fill layer, and forming an air gap in the space between the plurality of gates by removing the gap-fill layer.Type: GrantFiled: January 16, 2013Date of Patent: January 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Seok Na, Ji-Hwon Lee, Joong-Shik Shin, Chang-Sun Lee
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Patent number: 8324051Abstract: Methods of manufacturing NOR-type flash memory device include forming a tunnel oxide layer on a substrate, forming a first conductive layer on the tunnel oxide layer, forming first mask patterns parallel to one another on the first conductive layer in a y direction of the substrate, and selectively removing the first conductive layer and the tunnel oxide layer using the first mask patterns as an etch mask. Thus, first conductive patterns and tunnel oxide patterns are formed, and first trenches are formed to expose the surface of the substrate between the first conductive patterns and the tunnel oxide patterns. A photoresist pattern is formed to open at least one of the first trenches, and impurity ions are implanted using the photoresist pattern as a first ion implantation mask to form an impurity region extending in a y direction of the substrate. The photoresist pattern is removed.Type: GrantFiled: June 2, 2010Date of Patent: December 4, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Soo Song, Joong-Shik Shin
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Publication number: 20110177661Abstract: Methods of manufacturing NOR-type flash memory device include forming a tunnel oxide layer on a substrate, forming a first conductive layer on the tunnel oxide layer, forming first mask patterns parallel to one another on the first conductive layer in a y direction of the substrate, and selectively removing the first conductive layer and the tunnel oxide layer using the first mask patterns as an etch mask. Thus, first conductive patterns and tunnel oxide patterns are formed, and first trenches are formed to expose the surface of the substrate between the first conductive patterns and the tunnel oxide patterns. A photoresist pattern is formed to open at least one of the first trenches, and impurity ions are implanted using the photoresist pattern as a first ion implantation mask to form an impurity region extending in a y direction of the substrate. The photoresist pattern is removed.Type: ApplicationFiled: June 2, 2010Publication date: July 21, 2011Inventors: Young-Soo Song, Joong-Shik Shin
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Patent number: 6458709Abstract: A method for fabricating a repair fuse box of a semiconductor device is disclosed. An etching stop polysilicon layer formed at a belt shape in edge portions of a repair fuse box is broken during a repair etching process without substantial departure from prior art methods for fabricating a repair fuse box of a semiconductor device. Thus, it is possible to improve repair yield of the semiconductor device.Type: GrantFiled: January 2, 2001Date of Patent: October 1, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Eul Rak Kim, Joong Shik Shin
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Publication number: 20010015467Abstract: The present invention discloses a method for fabricating a transistor for a semiconductor device. The transistor requires and controls a high voltage, when using an anti-fuse circuit capable of carrying out a repair operation after packaging, thereby improving the operation property and yield of the device.Type: ApplicationFiled: January 2, 2001Publication date: August 23, 2001Inventors: Tae Hyoung Huh, Joong Shik Shin
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Publication number: 20010007794Abstract: A method for fabricating a repair fuse box of a semiconductor device is disclosed. An etching stop polysilicon layer formed at a belt shape in edge portions of a repair fuse box is broken during a repair etching process without substantial departure from prior art methods for fabricating a repair fuse box of a semiconductor device. Thus, it is possible to improve repair yield of the semiconductor device.Type: ApplicationFiled: January 2, 2001Publication date: July 12, 2001Inventors: Eul Rak Kim, Joong Shik Shin