Abstract: A semiconductor device may include a substrate including a first and a second row region, wherein a surface of the substrate is disposed in a first direction and a second direction perpendicular to the first direction, a first nanosheet structure on the first row region and including active segments disposed in the first direction, and the active segments having different widths in the second direction; and a second nanosheet structure on the second row region, the second nanosheet structure spaced apart from the first nanosheet structure in the second direction, and wherein the second nanosheet structure is symmetrical to the first nanosheet structure in the first direction. In a plan view, in each of the first and second nanosheet structures, transition regions between adjacent ones of the active segments have one of a same first angle and a second angle with respect to the first direction.

Abstract: A semiconductor device includes a substrate including first and second regions; a first active fin extending in a first direction on the first region; a second active fin extending in the first direction on the second region; an isolation pattern on the substrate between the first and second regions; a first gate structure on the first active fin, extending in a second direction perpendicular to the first direction, and onto an upper surface of the isolation pattern; and a second gate structure on the second active fin, extending in the second direction, and onto the upper surface of the isolation pattern, wherein the first gate structure includes a first portion having a first width and a second portion having a second width that is less than the first width, and the second gate structure includes a third portion having the first width and a fourth portion having the second width.

Abstract: A semiconductor device including: a substrate including a PMOS region, an N-well tap forming region, and a boundary region; PMOS field effect transistors on the PMOS region; an N-well tap region doped with N-type impurities in the N-well tap forming region; a first metal pattern connected to at least one impurity region of the PMOS field effect transistors, wherein the first metal pattern extends so that an end of the first metal pattern is positioned on the boundary region; a second metal pattern electrically connected to the N-well tap region, wherein the second metal pattern extends so that an end of the second metal pattern is positioned on the boundary region; a first contact plug on the first metal pattern; a second contact plug on the second metal pattern; and an upper wiring on the first and second contact plugs.

Abstract: A method of manufacturing a semiconductor device includes designing a semiconductor device layout using a design rule manual (DRM), in which design rules are recorded, and performing failure evaluation of a failure including at least one gate structure failure of a semiconductor device manufactured using the designed semiconductor device layout. The method further includes updating the DRM by updating the design rules recorded in the DRM, based on a result of the failure evaluation, redesigning the semiconductor device layout using the updated DRM, and manufacturing the semiconductor device using the redesigned semiconductor device layout.

Abstract: A semiconductor device includes a substrate including an active region, a first gate line and a second gate line in the active region, a first source/drain contact pattern in the active region at one side of the first gate line, a second source/drain contact pattern in the active region at one side of the second gate line, and a dummy source/drain contact pattern in the active region between the first gate line and the second gate line. The first gate line and the second gate line may be spaced apart from each other in the first direction and may extend in the second direction. The second direction may cross the first direction. A size of the dummy source/drain contact pattern may be less than a size of the first source/drain contact pattern and a size of the second source/drain contact pattern.

Abstract: The present invention relates to a synthetic catalyst of the following formula (A) which can selectively recognize and cleave a specific protein among a protein mixture, and to a method for selective cleavage of a target protein using the same: