Patents by Inventor Joongwon SHIN
Joongwon SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145317Abstract: A semiconductor package, includes: a base chip having a front surface and a back surface opposite to the front surface, the base chip including bump pads, wafer test pads, and package test pads, disposed on the front surface; connection structures disposed on the front surface of the base chip and connected to the bump pads; and semiconductor chips stacked on the back surface of the base chip, wherein each of the wafer test pads is smaller than the package test pads.Type: ApplicationFiled: June 15, 2023Publication date: May 2, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Joongwon Shin, Jongmin Lee, Sungyun Woo, Nara Lee, Yeonjin Lee, Jimin Choi
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Publication number: 20240071923Abstract: A semiconductor device may include lower metal wirings on a substrate, a first upper insulating interlayer on the lower metal wirings, a first upper wiring including a first upper via in the first upper insulating interlayer and a first upper metal pattern on the first upper insulating interlayer. The semiconductor device may also include a second upper insulating interlayer on the first upper insulating interlayer, an uppermost wiring including an uppermost via in the second upper insulating interlayer, an uppermost metal pattern on the second upper insulating interlayer, and an oxide layer for supplying hydrogen on the second upper insulating interlayer. The lower metal wirings may be stacked in a plurality of layers. The oxide layer for supplying hydrogen may cover the uppermost wiring. A thickness of the uppermost via may be less than 40% of a thickness of the uppermost metal pattern.Type: ApplicationFiled: June 14, 2023Publication date: February 29, 2024Inventors: Minjun SONG, Jongmin LEE, Joongwon SHIN, Nara LEE, Jimin CHOI
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Publication number: 20240069093Abstract: Provided are a semiconductor chip with a reduced thickness and improved reliability, and a semiconductor package including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, an integrated device layer on the semiconductor substrate, a multi-wiring layer on the integrated device layer, and a pad metal layer of a plurality of pad metal layers on the multi-wiring layer, and having test pads defined therein. The pad metal layers extend in a first direction parallel to a top surface of the semiconductor substrate or in a second direction perpendicular to the first direction. A test pad is a central portion of the pad metal layer and, and an outer portion of the pad metal layer excluding the test pad overlaps the wires in a third direction perpendicular to the top surface of the semiconductor substrate.Type: ApplicationFiled: February 27, 2023Publication date: February 29, 2024Inventors: Sehyun Hwang, Jongmin Lee, Joongwon Shin, Jimin Choi
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Publication number: 20240038675Abstract: A semiconductor device may include a plurality of chip regions on a substrate, at least one scribe lane surrounding each of the plurality of chip regions on the substrate, a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions, and a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane.Type: ApplicationFiled: May 8, 2023Publication date: February 1, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Jimin CHOI, Joongwon SHIN, Sungyun WOO, Yeonjin LEE, Jongmin LEE, Sehyun HWANG
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Patent number: 11616018Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.Type: GrantFiled: August 10, 2021Date of Patent: March 28, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Juik Lee, Joongwon Shin, Jihoon Chang, Junghoon Han, Junwoo Lee
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Patent number: 11587897Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a conductive pad on a first surface of the semiconductor substrate, a passivation layer on the first surface of the semiconductor substrate, the passivation layer having a first opening that exposes the conductive pad, an organic dielectric layer on the passivation layer, the organic dielectric layer having a second opening, and a bump structure on the conductive pad and in the first and second openings. The organic dielectric layer includes a material different from a material of the passivation layer. The second opening is spatially connected to the first opening and exposes a portion of the passivation layer. The bump structure includes a pillar pattern in contact with the passivation layer and the organic dielectric layer.Type: GrantFiled: January 7, 2021Date of Patent: February 21, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joongwon Shin, Yeonjin Lee, Inyoung Lee, Jimin Choi, Jung-Hoon Han
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Publication number: 20210375759Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.Type: ApplicationFiled: August 10, 2021Publication date: December 2, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Juik LEE, Joongwon SHIN, Jihoon CHANG, Junghoon HAN, Junwoo LEE
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Publication number: 20210305188Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a conductive pad on a first surface of the semiconductor substrate, a passivation layer on the first surface of the semiconductor substrate, the passivation layer having a first opening that exposes the conductive pad, an organic dielectric layer on the passivation layer, the organic dielectric layer having a second opening, and a bump structure on the conductive pad and in the first and second openings. The organic dielectric layer includes a material different from a material of the passivation layer. The second opening is spatially connected to the first opening and exposes a portion of the passivation layer. The bump structure includes a pillar pattern in contact with the passivation layer and the organic dielectric layer.Type: ApplicationFiled: January 7, 2021Publication date: September 30, 2021Inventors: JOONGWON SHIN, YEONJIN LEE, INYOUNG LEE, JIMIN CHOI, JUNG-HOON HAN
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Patent number: 11133253Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.Type: GrantFiled: May 28, 2020Date of Patent: September 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Juik Lee, Joongwon Shin, Jihoon Chang, Junghoon Han, Junwoo Lee
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Publication number: 20210104462Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.Type: ApplicationFiled: May 28, 2020Publication date: April 8, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Juik LEE, Joongwon SHIN, Jihoon CHANG, Junghoon HAN, Junwoo LEE