Abstract: A semiconductor device includes a peripheral circuit structure including a first substrate and circuit elements on the first substrate; and a memory cell structure including a second substrate on the first substrate, a first horizontal conductive layer on the second substrate, a second horizontal conductive layer on the first horizontal conductive layer, gate electrodes spaced apart from each other and stacked on the second horizontal conductive layer, channel structures penetrating through the gate electrodes, and separation regions penetrating the gate electrodes, extending, and spaced apart from each other.

Abstract: A switch for controlling the throughput of a signal between a pair of input channels and a pair of output channels is provided which receives an input signal from each of the pair of input channels. The switch transmits an output signal to each of the pair of output channels. Four line channels are provided within the switch. Each of the four line channels connects one of the pair of input channels and one of the pair of output channels. Four line channel switches are also provided, one line channel switch provided on each of the line channels. Each of the four line channel switches is controlled by a signal to open or close the four line channels.

Abstract: A spur-free sigma delta modulator analog-to-digital converter for converting an analog input signal to a digital output signal is provided. A race Josephson junction is provided between the pulse generator and the integrating inductor. The race Josephson junction emits a voltage pulse in response to every sampling pulse. This voltage pulse kills any retained persisting current in the integrating inductor. By adding the race Josephson junction, nonlinearities in the converter are eliminated.A multiple flux quanta feedback generator for creating a multiple digital pulse feedback in response to an input signal is provided. A quantizer connected to the input inductor produces a pulse when the current produced by the input inductor exceeds a predetermined amount. A splitter is connected to the quantizer for producing output pulses. In order to produce 2.sup.n output pulses, 2.sup.n -1 splitters are required. Each of the splitters produces two output pulses in response to a single pulse produced by the quantizer.

Abstract: A serial multiplier for multiplying two n-bit numbers is provided in which a shift register having a total of n destructive read out cells contains a separate bit of a first multiplicand in each cell. A string of (2n-1) non-destructive read out cells is provided to receive the second multiplicand. Each of the first n cells of the string of non-destructive readout cells contain a separate bit of the second multiplicand. Each bit of the first multiplicand is serially multiplied with the series of bits of said second multiplicand. After each such multiplication, each bit of the second multiplicand is moved to the next adjacent cell. The partial product of the multiplication is stored in a string of 2n T flip-flop cells. Each of the T flip-flop cells has a carry path to the next adjacent T flip-flop cell. Timing means are provided to regulate and initiate the multiplication.