Abstract: Provided are a method and apparatus for processing a division operation. The method includes acquiring input data, detecting reference data related to a division operation corresponding to the acquired input data, from a cache memory in which data related to at least one division operation is pre-stored, selecting any one operator from among a plurality of operators identified according to at least one of a processable number of data bits and a calculation type, based on a difference between the detected reference data and the input data, and acquiring a result of performing division operation on the input data from the selected operator.

Abstract: A method of decoding a bitstream, a method of accelerating an inverse transform, an apparatus, a video decoder, and a non-transitory computer-readable recording medium are provided. The method includes receiving an encoded bitstream, extracting transformation coefficients from the received bitstream, determining a position of a block including at least one nonzero transformation coefficient from among the extracted transformation coefficients, and generating decoded video data by inverse-transforming transformation coefficients in the block by using the determined position.

Abstract: It is an aspect of the present disclosure to provide an image processing apparatus, a display apparatus and a method of controlling of the display apparatus capable of preventing a rapid decrease in the image quality of image data. In accordance with an example aspect of the present disclosure, a display apparatus comprises: a plurality of image processing modules, each image processing module configured to perform an image processing process; a controller configured to output image data processed by any one image processing module of the plurality of image processing modules, based on state information of the plurality of image processing modules; and a display configured to display the output image data.

Abstract: A processor includes: at least one operator; and at least one macro instruction processing unit configured to share the at least one operator, wherein the at least one macro instruction processing unit is configured to execute a macro instruction with respect to input data by using the at least one operator to output result data, and to control the at least one operator to perform an operation included in the macro instruction, and the at least one macro instruction processing unit comprises: a scheduler configured to manage schedules of the at least one operator and output input data and a control signal to the at least one operator; and a controller configured to control the scheduler to execute the macro instruction and to receive the result data from the scheduler.

Abstract: Provided is a shared resource access arbitration method of a shared resource access arbitration apparatus, the shared resource access arbitration method including: receiving, from at least one master apparatus, buffer status information related to a buffer included in the at least one master apparatus; determining, based on the received buffer status information, priorities of shared resource access requests received from a plurality of master apparatuses including the at least one master apparatus; and granting, according to the determined priorities of the shared resource access requests, one of the shared resource access requests having a high priority.

Abstract: A method for distributing a load, according to one embodiment, includes: identifying characteristics of each of frames included in a received bit stream; and distributing loads of a plurality of cores based on the characteristics of each of the frames whenever the frames are decoded.

Abstract: Provided are a method and apparatus for processing a division operation. The method includes acquiring input data, detecting reference data related to a division operation corresponding to the acquired input data, from a cache memory in which data related to at least one division operation is pre-stored, selecting any one operator from among a plurality of operators identified according to at least one of a processable number of data bits and a calculation type, based on a difference between the detected reference data and the input data, and acquiring a result of performing division operation on the input data from the selected operator.

Abstract: Provided is a shared resource access arbitration method of a shared resource access arbitration apparatus, the shared resource access arbitration method including: receiving, from at least one master apparatus, buffer status information related to a buffer included in the at least one master apparatus; determining, based on the received buffer status information, priorities of shared resource access requests received from a plurality of master apparatuses including the at least one master apparatus; and granting, according to the determined priorities of the shared resource access requests, one of the shared resource access requests having a high priority.

Abstract: It is an aspect of the present disclosure to provide an image processing apparatus, a display apparatus and a method of controlling of the display apparatus capable of preventing a rapid decrease in the image quality of image data. In accordance with an example aspect of the present disclosure, a display apparatus comprises: a plurality of image processing modules, each image processing module configured to perform an image processing process; a controller configured to output image data processed by any one image processing module of the plurality of image processing modules, based on state information of the plurality of image processing modules; and a display configured to display the output image data.

Abstract: A digital signal processor (DSP) interface apparatus capable of variably setting an interconnection between a DSP and a plurality of hardware devices and a method of controlling the same are provided. The DSP interface apparatus includes a path setter configured to set a data transmission path between at least one of a plurality of hardware devices and a DSP; and a controller configured to control the path setter to set the data transmission path by connecting at least one of a plurality of operation parts and a memory of the DSP and at least one of the plurality of hardware devices based on predetermined configuration information.

Abstract: A processor includes: at least one operator; and at least one macro instruction processing unit configured to share the at least one operator, wherein the at least one macro instruction processing unit is configured to execute a macro instruction with respect to input data by using the at least one operator to output result data, and to control the at least one operator to perform an operation included in the macro instruction, and the at least one macro instruction processing unit comprises: a scheduler configured to manage schedules of the at least one operator and output input data and a control signal to the at least one operator; and a controller configured to control the scheduler to execute the macro instruction and to receive the result data from the scheduler.

Abstract: A method and apparatus for applying a tile size adaptively based on a size of a coding unit. An image processing apparatus may detect a size of a largest coding unit (LCU) used in encoding of a video from a header of a bitstream, may determine a tile size adaptively based on the detected size of the LCU, and may decode the bitstream in units of the LCU based on the determined tile size.

Abstract: A method of manufacturing an inner case for a refrigerator includes disposing a heated inner case sheet above a mold in a chamber, disposing at least one of screw accommodation member on an external surface of the mold, facing the inner case sheet, curving the inner case sheet to be convex toward an opposite side to the mold, moving the mold toward an internal side of the inner case sheet, and adsorbing the inner case sheet onto the external surface of the mold to form the inner case sheet to correspond to a shape of the mold and insert-molding the screw accommodation member into the inner case sheet.

Abstract: A reconfigurable processor and an operation method of the reconfigurable processor may include: a status register configured to store a status value used to determine at least one execution mode in a processor; a parallel processing scheduler configured to schedule at least one of a very long instruction word (VLIW) logic and a coarse grained architecture (CGA) logic to be used based on the stored status value; a VLIW register configured to store processed data according to the VLIW logic; and a CGA register configured to store processed data according to the CGA logic.

Abstract: An arithmetic processing apparatus and method for high speed processing of an application are provided. The arithmetic processing apparatus may include a program control unit to store operation processing information necessary for application operation in a communication channel by executing an application code, and an operation processing unit to process the application operation using the operation processing information stored in the communication channel.

Abstract: A method for distributing a load, according to one embodiment, includes: identifying characteristics of each of frames included in a received bit stream; and distributing loads of a plurality of cores based on the characteristics of each of the frames whenever the frames are decoded.

Abstract: An encoding/decoding apparatus and method for parallel correction of in-loop pixels based on complexity using a video parameter may include a complexity measuring unit to measure a complexity of an in-loop pixel correction process, using video codec parameter information, in a video codec, and a core allocating unit to evenly distribute jobs associated with the in-loop pixel correction process, using the measured complexity.

Abstract: A method of decoding a bitstream, a method of accelerating an inverse transform, an apparatus, a video decoder, and a non-transitory computer-readable recording medium are provided. The method includes receiving an encoded bitstream, extracting transformation coefficients from the received bitstream, determining a position of a block including at least one nonzero transformation coefficient from among the extracted transformation coefficients, and generating decoded video data by inverse-transforming transformation coefficients in the block by using the determined position.

Abstract: An apparatus and a method for dividing image data into partition slices and encoding and decoding the image data based on a correlation between macroblocks are provided. The macroblocks may be decoded in parallel and thus, it is possible to improve an overall image quality and processing speed.

Abstract: An apparatus and method sequentially parses bitstreams based on a removal of an Emulation Prevention Byte (EPB). The apparatus and method may detect an EPB pattern from among sequentially input bitstreams, may store the bitstreams, may store a processed bitstream where the EPB pattern is removed, among the bitstreams, and may select an output of a register buffer based on an input of a buffer selection flag.